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rev. 4679c?4bmcu?03/04 features 8 k 8-bit eeprom eeprom programmable options read protection for the eeprom program memory 256 4-bit ram 2 32 16-bit data eeprom up to seven external/internal interrupt sources eight hardware and software interrupt priorities 16 bi-directional i/os wide supply-voltage range (1.8 v to 6.5 v) very low sleep current (< 1 a) synchronous serial interface (2-wire, 3-wire) multifunction timer/counter with prescaler/interval timer voltage monitoring inclusive lo_bat detect watchdog, por and brown-out function description the ATAM894 is a member of the atmel?s family of 4-bit single chip microcontrollers with 8 k 8-bit eeprom program memory. it is based on the 4-k mtp version atam893 and fully compatible with this mtp and the rom versions atar090/890 and atar092/892. figure 1. block diagram voltage monitor external input marc4 utcm osc1 osc2 i/o bus eeprom 8 k x 8 bit ram 4-bit cpu core 256 x 4 bit v dd data direction + alternate function data direction + interrupt control port 4 port 5 data dir. + alt. function port 6 timer 3 brown-out protect. reset clock management timer 1 watchdog timer timer 2 serial interface port 1 p o r t 2 d a t a d i r e c t i o n t2o sd sc t3o t3i bp10 bp13 bp20/nte bp21 bp22 bp23 bp40 int3 sc bp41 vmi t2i bp42 t2o bp43 int3 sd bp50 int6 bp51 int6 bp52 int1 bp53 int1 bp60 t3o bp63 t3i rc oscillators crystal oscillators vmi with prescaler ssi external clock input interval- and timer/counter t2i eeprom 2 x 32 x 16 bit modulator 2 modulator 3 demodulator sd sc v ss 8k-flash microcontroller ATAM894
2 ATAM894 4679c?4bmcu?03/04 pin configuration figure 2. pinning sso24 package 1 2 3 4 5 6 7 8 10 9 23 18 17 16 14 15 13 12 11 24 21 22 19 20 bp52/int1 bp51/int6 bp50/int6 osc1 osc2 bp60/t3o bp40/int3/sc bp53/int1 bp10 vdd nc nc bp41/vmi/t2i bp23 bp22 bp21 bp20/nte bp63/t3i bp43/int3/sd bp42/t2o bp13 vss nc nc pin description pin symbol type function alternate function reset state 1 nc ? not connected ? ? 2 nc ? not connected ? ? 3 vdd ? supply voltage ? na 4 bp40 i/o bi-directional i/o line of port 4.0 sc-serial clock or int3 external interrupt input input 5 bp53 i/o bi-directional i/o line of port 5.3 int1 external interrupt input input 6 bp52 i/o bi-directional i/o line of port 5.2 int1 external interrupt input input 7 bp51 i/o bi-directional i/o line of port 5.1 int6 external interrupt input input 8 bp50 i/o bi-directional i/o line of port 5.0 int6 external interrupt input input 9 osc1 i oscillator input 4-mhz crystal input or 32-khz crystal input or external clock input or external trimming resistor input input 10 osc2 o oscillator output 4-mhz crystal output or 32-khz crystal output or external clock input input 11 bp60 i/o bi-directional i/o line of port 6.0 t3o timer 3 output input 12 bp10 i/o bi-directional i/o line of port 1.0 ? input 13 bp13 i/o bi-directional i/o line of port 1.3 ? input 14 bp63 i/o bi-directional i/o line of port 6.3 t3i timer 3 input input 15 bp20 i/o bi-directional i/o line of port 2.0 nte test mode enable, see section ?master reset? input 16 bp21 i/o bi-directional i/o line of port 2.1 ? input 17 bp22 i/o bi-directional i/o line of port 2.2 ? input 18 bp23 i/o bi-directional i/o line of port 2.3 ? input
3 ATAM894 4679c?4bmcu?03/04 introduction the ATAM894 is a member of atmel?s family of 4-bit single-chip microcontrollers. instead of rom it contains eeprom, ram, parallel i/o ports, two 8-bit programmable multifunction timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated rc-, 32-khz and 4-mhz crystal oscillators. differences between ATAM894 and atarx90/x92 program memory the program memory of the mtp device is realized as an eeprom. the memory size for user programs is 8192 bytes. it is programmed as 258 32-byte blocks of data. the implemented lock bit function is user selectable and protects the device from unautho- rized read out of the program memory. configuration memory an additional area of 64 bytes of the eeprom is used to store information about the hardware configuration. all the options that are selectable for the rom versions are available to the user. this includes not only the different port options but also the possi- bilities to select different capacitors for osc1 and osc2, the option to enable or disable the hardlock for the watchdog, the option to select osc2 instead of osc1 as external clock input and the option to enable the external clock monitor as a reset source. acti- vating the options is performed by the reset circuitry. reset starts a download sequence to transfer the information from the memory into a shift register (configuration register). data memory the ATAM894 contains an internal data eeprom that is organized as two pages of 32 16 bit. if it is necessary to be compatible with the rom parts, only one page must be used with the flash part. also for compatibility reasons the access to the eeprom is handled via the mcl (serial interface) as in the corresponding rom parts. a behavioral difference that only needs to be considered for error handling can be seen, when the communication via the mcl is not terminated correctly. a missing stop condition leads to a significantly higher current consumpti on for the rom parts compared to the flash parts. a slightly different concept for the read amplifiers of the memory makes the flash part more tolerant in terms of communication errors. reset function during each reset (power-on or brown-out) the configuration register is reset and reloaded with the data from the configuration memory. this leads to a slightly different behavior compared to the rom versions. both devices switch their i/os to input during reset but the rom part has the mask selected pull-up or pull-down resistors active while the mtp has them removed until the download is finished. 19 bp41 i/o bi-directional i/o line of port 4.1 vmi voltage monitor input or t2i external clock input timer 2 input 20 bp42 i/o bi-directional i/o line of port 4.2 t2o timer 2 output input 21 bp43 i/o bi-directional i/o line of port 4.3 sd serial data i/o or int3 external interrupt input input 22 vss ? circuit ground ? input 23 nc ? not connected ? ? 24 nc ? not connected ? ? pin description (continued) pin symbol type function alternate function reset state
4 ATAM894 4679c?4bmcu?03/04 marc4 architecture general description the marc4 microcontroller consists of an advanced stack-based, 4-bit cpu core and on-chip peripherals. the cpu is based on the harvard architecture with physically sep- arate program memory (rom) and data memory (ram). three independent buses, the instruction bus, the memory bus and the i/o bus, are used for parallel communication between rom, ram and peripherals. this enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. the extremely powerful integrated interrupt controller with associ- ated eight prioritized interrupt levels supports fast and efficient processing of hardware events. the marc4 is designed for the high-level programming language qforth. the core includes both, an expression and a return stack. this architecture enables high-level language programming without any loss of efficiency or code density. figure 3. marc4 core components of marc4 core the core contains rom, ram, alu, program counter, ram address registers, instruc- tion decoder and interrupt controller. the following sections describe each functional block in more detail. instruction decoder ccr tos alu ram pc rp sp x y program 256 x 4-bit marc4 core clock reset sleep memory bus i/o bus instruction bus reset system clock interrupt controller on-chip peripheral modules memory
5 ATAM894 4679c?4bmcu?03/04 program memory the program memory (eeprom) is electrically programmable and erasable with the customer application program. the program memory is addressed by a 12-bit wide pro- gram counter and an additional rom bank register, thus predefining a maximum linear adressable program bank size of 4 kbytes. the upper 2 kbytes may be exchanged by rom banking, thus allowing to address a maximum of 10 kbytes user program. 8 kbytes of program memory are available within the ATAM894. the lowest user (eep)rom address segment is taken up by a 512-byte zero page which contains pre- defined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (scall). the corresponding memory map is shown in figure 4. look-up tables of constants can also be held in rom and are accessed via the marc4?s built-in table instruction. figure 4. rom map rom banking for customers programming with qforth the bank switching is fully supported by the compiler. the marc4 switches from one rom bank to another by writing the new bank number to the rom bank register (rbr). conventional program space (power-up bank) resides in rom bank 0. each rom ba nk consists of a 2 kbyte address space whereby the lowest 2 kbyte, the base bank, is common to all banks, so that addresses between 000h and 7ffh always access the same rom data (see figure 4). when rom banking is used, the compiler will, if necessary, insert program code to save and restore the condition of the rbr on bank switching. ram the ATAM894 contains 256 4-bit wide static random access memory (ram). it is used for the expression stack, the return stack and data memory for variables and arrays. the ram is addressed by any of the four 8-bit wide ram address registers sp, rp, x and y. expression stack the 4-bit wide expression stack is addressed with the expression stack pointer (sp). all arithmetic, i/o and memory reference operations take their operands from, and return their results to the expression stack. the marc4 performs the operations with the top of stack items (tos and tos-1). the tos register contains the top element of the expres- sion stack and works in the same way as an accumulator. this stack is also used for passing parameters between subroutines and as a scratch pad area for temporary stor- age of data. zero page base bank bank 1 bank 2 bank 4 bank 3 000h port d: 00xxb fffh 800h 7ffh port d: 11xxb port d: 10xxb port d: 01xxb 000h 1ffh zero page $autosleep $reset int0 int7 int6 int5 int4 int3 int2 int1
6 ATAM894 4679c?4bmcu?03/04 return stack the 12-bit wide return stack is addressed by the return stack pointer (rp). it is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. the return stack can also be used as a temporary storage area. the marc4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. the two stacks within the ram have a user definable location and maximum depth. figure 5. ram map registers the marc4 controller has seven programmable registers and one condition code regis- ter. they are shown in the following programming model. program counter (pc) the program counter is a 12-bit register which contains the address of the next instruc- tion to be fetched from the rom. instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. for linear code (no calls or branches) the program counter is incremented with every instruction cycle. if a branch-, call-, return-instruction or an interrupt is executed, the program counter is loaded with a new address. the program counter is also used with the table instruction to fetch 8-bit wide rom constants. ram fch 00h autosleep ffh 03h 04h x y sp rp tos-1 expression stack return stack global variables ram address register: 07h (256 x 4-bit) global variables 4-bit tos tos-1 tos-2 30 sp expression stack return stack 0 11 12-bit rp v
7 ATAM894 4679c?4bmcu?03/04 figure 6. programming model rom banking register (rbr) the rom banking register is a 4-bit register whereby the ATAM894 only uses 2 bit. this register indicates which rom bank is presently being addressed. the rbr is accessed with a standard qforth peripheral read or write instruction (in or out, port address 'd' hex). ram address registers the ram is addressed with the four 8-bit wide ram address registers: sp, rp, x and y. these registers allow access to any of the 256 ram nibbles. expression stack pointer (sp) the stack pointer contains the address of the next-to-top 4-bit item (tos-1) of the expression stack. the pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. every post-decre- ment operation moves the item (tos-1) to the tos register before the sp is decremented. after a reset the stack pointer ha s to be initialized with ?>sp s0? to allo- cate the start address of the expression stack area. return stack pointer (rp) the return stack pointer points to the top element of the 12-bit wide return stack. the pointer automatically pre-increments if an el ement is moved onto the stack, or it post- decrements if an element is removed from the stack. the return stack pointer incre- ments and decrements in steps of 4. this means that every time a 12-bit element is stacked, a 4-bit ram location is left unwritten. this location is used by the qforth compiler to allocate 4-bit variables. after a reset the return stack pointer has to be initial- ized via ?>rp fch?. ram address registers (x and y) the x and y registers are used to address any 4-bit item in the ram. a fetch operation moves the addressed nibble onto the tos. a store operation moves the tos to the addressed ram location. by using either the pre-increment or post-decrement address- ing mode arrays in the ram can be compared, filled or moved. tos ccr 0 3 0 3 0 7 0 7 7 0 11 rp sp x y pc -- b i program counter return stack pointer expression stack pointer ram address register (x) ram address register (y) top of stack register condition code register carry/borrow branch interrupt enable reserved 0 7 c 0 0 rbr 0 3 rom banking register -- -- 0
8 ATAM894 4679c?4bmcu?03/04 top of stack (tos) the top of stack register is the accumulator of the marc4. all arithmetic/logic, memory reference and i/o operations use this register. the tos register receives data from the alu, rom, ram or i/o bus. condition code register (ccr) the 4-bit wide condition code re gister contains the branch, the carry and the interrupt enable flag. these bits indicate the current state of the cpu. the ccr flags are set or reset by alu operations. the instructions set_bcf, tog_bf, ccr! and di allow direct manipulation of the condition code register. carry/borrow (c) the carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit (alu) occurred during the last arithmetic operation. during shift and rotate opera- tions, this bit is used as a fifth bit. boolean operations have no affect on the c-flag. branch (b) the branch flag controls the conditional pr ogram branching. should the branch flag have been set by a previous instruction, a conditional branch will cause a jump. this flag is affected by arithmetic, logic, shift, and rotate operations. interrupt enable (i) the interrupt enable flag globally enables or disables the triggering of all interrupt rou- tines with the exception of the non-maskable reset. after a reset or on executing the di instruction, the interrupt enable flag is reset, thus disabling all interrupts. the core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an ei or sleep instruction. alu the 4-bit alu performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (tos and tos-1) and returns the result to the tos. the alu operations affect the carry/borrow and branch flag in the condition code register (ccr). figure 7. alu zero-address operations i/o bus the i/o ports and the registers of the peripheral modules are i/o mapped. all communi- cation between the core and the on-chip peripherals takes place via the i/o bus and the associated i/o control. with the marc4 in and out instructions the i/o bus allows a direct read or write access to one of the 16 primary i/o addresses. more about the i/o access to the on-chip peripherals is described in the section ?peripheral modules?. the i/o bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interfac e for the marc4 emulation (see section ?emulation?). tos-1 ccr ram tos-2 sp tos-3 tos alu tos-4
9 ATAM894 4679c?4bmcu?03/04 instruction set the marc4 instruction set is optimized for the high level programming language qforth. many marc4 instructions are qforth words. this enables the compiler to generate a fast and compact program code. the cpu has an instruction pipeline allow- ing the controller to prefetch an instruction from program memory at the same time as the present instruction is being executed. the marc4 is a zero address machine, the instructions containing only the operation to be performed and no source or destination address fields. the operations are implicitly performed on the data placed on the stack. there are one and two byte instructions which are executed within 1 to 4 machine cycles. a marc4 machine cycle is made up of two system clock cycles (syscl). most of the instructions are only one byte long and are executed in a single machine cycle. for more information refer to the ?marc4 programmer's guide?. interrupt structure the marc4 can handle interrupts with eight different priority levels. they can be gener- ated from the internal and external interrupt sources or by a software interrupt from the cpu itself. each interrupt level has a hard-wired priority and an associated vector for the service routine in the program memory (see table 1 on page 10). the programmer can postpone the processing of interrupts by resetting the interrupt enable flag (i) in the ccr. an interrupt occurrence will still be registered, but the interrupt routine only started after the i flag is set. all interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section ?peripheral modules?). interrupt processing for processing the eight interrupt levels, the marc4 includes an interrupt controller with two 8-bit wide ?interrupt pending? and ?interrupt active? registers. the interrupt controller samples all interrupt requests during every non-i/o instruction cycle and latches these in the interrupt pending register. if no higher priority interrupt is present in the interrupt active register, it signals the cpu to interrupt the current program execution. if the inter- rupt enable bit is set, the processor enters an interrupt acknowledge cycle. during this cycle a short call (scall) instruction to the service routine is executed and the current pc is saved on the return stack. an interrupt service routine is completed with the rti instruction. this instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. when the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. the execution of the interrupt is delayed until the interrupt enable flag is set again. note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). it should also be noted that automatic stacking of the rbr is not carried out by the hard- ware and so if rom banking is used, the rbr must be stacked on the expression stack by the application program and restored before the rti. after a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active registers are all reset. interrupt latency the interrupt latency is the time from the occurrence of the interrupt to the interrupt ser- vice routine being activated. in marc4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core).
10 ATAM894 4679c?4bmcu?03/04 figure 8. interrupt handling 7 6 5 4 3 2 1 0 priority level int5 active int7 active int2 pending swi0 int2 active int0 pending int0 active int2 rti rti int5 int3 active int3 rti rti rti int7 time main / autosleep main/ autosleep table 1. interrupt priority table interrupt priority rom address interrupt opcode function int0 lowest 040h c8h (scall 040h) software interrupt (swi0) int1 | 080h d0h (scall 080h) external hardware interrupt, any edge at bp52 or bp53 int2 | 0c0h d8h (scall 0c0h) timer 1 interrupt int3 | 100h e8h (scall 100h) ssi interrupt or external hardware interrupt at bp40 or bp43 int4 | 140h e8h (scall 140h) timer 2 interrupt int5 | 180h f0h (scall 180h) timer 3 interrupt int6 1c0h f8h (scall 1c0h) external hardware interrupt, at any edge at bp50 or bp51 int7 highest 1e0h fch (scall 1e0h) voltage monitor (vm) interrupt
11 ATAM894 4679c?4bmcu?03/04 software interrupts the programmer can generate interrupts by using the software interrupt instruction (swi) which is supported in qforth by predefined macros named swi0...swi7. the software triggered interrupt operates exactly like any hardware triggered interrupt. the swi instruction takes the top two elements from the expression stack and writes the cor- responding bits via the i/o bus to the interrupt pending register. therefore, by using the swi instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution. hardware interrupts in the ATAM894, there are eleven hardware interrupt sources with seven different lev- els. each source can be masked individually by mask bits in the corresponding control registers. an overview of the possible hardw are configurations is shown in table 2 on page 11. master reset the master reset forces the cpu into a well-defined condition. it is unmaskable and is activated independent of the current program stat e. it can be triggered by either initial supply power-up, a short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an external input clock supervisor stage (see figure 9 on page 12). a master reset activation will reset the in terrupt enable flag, the interrupt pending register and the interrupt active register. during the power-on reset phase the i/o bus control signals are set to reset mode thereby initializing all on-chip peripherals. all bi-directional ports are set to input mode. attention: during any reset phase, the bp20/nte input is driven towards v dd by a strong pull-up transistor. this pin must not be pulled down to v ss during reset by any external circuitry representing a resistor of less than 150 k ? . releasing the reset results in a short call instruction (opcode c1h) to the eeprom address 008h. this activates the initializatio n routine $reset which in turn has to ini- tialize all necessary ram variables, stack pointers and peripheral configuration registers (see table 9). table 2. hardware interrupts interrupt interrupt mask interrupt source register bit int1 p5cr p52m1, p52m2 p53m1, p53m2 any edge at bp52 any edge at bp53 int2 t1m t1im timer 1 int3 sisc sim ssi buffer full/empty or bp40/bp43 interrupt int4 t2cm t2im timer 2 compare match/overflow int5 t3cm1 t3cm2 t3c t3im1 t3im2 t3eim timer 3 compare register 1 match timer 3 compare register 2 match timer 3 edge event occurs (t3i) int6 p5cr p50m1, p50m2 p51m1, p51m2 any edge at bp50 any edge at bp51 int7 vcm vim external/internal voltage monitoring
12 ATAM894 4679c?4bmcu?03/04 figure 9. reset configuration power-on reset and brown-out detection the ATAM894 has a fully integrated power-on reset and brown-out detection circuitry. for reset generation no external components are needed. these circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. a reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power down mode is activated (the core is in sleep mode and the peripheral clock is stopped). in this power-down mode the brown-out detection is disabled. two values for the brown-out voltage threshold are programmable via the bot bit in the sc register. a power-on reset pulse is generated by a v dd rise across the default bot voltage level (1.7 v). a brown-out reset pulse is generated when v dd falls below the brown-out volt- age threshold. two values for the brown-out voltage threshold are programmable via the bot bit in the sc register. when the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. when it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. for further details, see the electrical specification and the sc register description for bot programming. reset timer v dd cl power-on reset internal reset res cl = syscl/4 brown-out detection watch- dog cwd res ext. clock supervisor exin pull-up nrst v dd v ss v dd v ss
13 ATAM894 4679c?4bmcu?03/04 figure 10. brown-out detection note: bot = 1, low brown-out voltage threshold 1.7 v (is reset value). bot = 0, high brown-out voltage threshold 2.0 v. watchdog reset the watchdog's function can be enabled at the wdc register and triggers a reset with every watchdog counter overflow. to s uppress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (cwd). the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. external clock supervisor the external input clock supervisor function can be enabled if the external input clock is selected within the cm- and sc registers of the clock module. the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. voltage monitor the voltage monitor consists of a comparator with an internal voltage reference. it is used to supervise the supply voltage or an external voltage at the vmi pin. the compar- ator for the supply voltage has three inte rnal programmable thresholds: one lower threshold (2.2 v), one middle threshold (2.6 v) and one higher threshold (3.0 v). for external voltages at the vmi pin, the comparator threshold is set to v bg = 1.3 v. the vms bit indicates if the supervised voltage is below (vms = 0) or above (vms = 1) this threshold. an interrupt can be generated when the vms bit is set or reset to detect a ris- ing or falling slope. a voltage monitor interrupt (int7) is enabled when the interrupt mask bit (vim) is reset in the vmc register. v dd cpu reset t bot = 1 2.0 v 1.7 v bot = 0 t d = 1.5 ms (typically) t d t d t d cpu reset
14 ATAM894 4679c?4bmcu?03/04 figure 11. voltage monitor voltage monitor control/ status register vm2: v oltage monitor m ode bit 2 vm1: v oltage monitor m ode bit 1 vm0: v oltage monitor m ode bit 0 v dd vm2 voltage monitor vm1 vm0 vim vms - - res out in bp41/ vmi int7 vmc: vmst: primary register address: ?f?hex bit 3 bit 2 bit 1 bit 0 vmc: write vm2 vm1 vm0 vim reset value: 1111b vmst: read ? ? reserved vms reset value: xx11b table 3. voltage monitor modes vm2 vm1 vm0 function 1 1 1 disable voltage monitor 110 external (vim input), internal reference threshold (1.3 v), interrupt with negative slope 1 0 1 not allowed 100 external (vmi input), internal reference threshold (1.3 v), interrupt with positive slope 011 internal (supply voltage), high threshold (3.0 v), interrupt with negative slope 010 internal (supply voltage), middle threshold (2.6 v), interrupt with negative slope 001 internal (supply voltage), low threshold (2.2 v), interrupt with negative slope 0 0 0 not allowed
15 ATAM894 4679c?4bmcu?03/04 vim v oltage i nterrupt m ask bit vim = 0, voltage monitor interrupt is enabled vim = 1, voltage monitor interrupt is disabled vms v oltage m onitor s tatus bit vms = 0, the voltage at the comparator input is below v ref vms = 1, the voltage at the comparator input is above v ref figure 12. internal supply voltage supervisor figure 13. external input voltage supervisor clock generation clock module the ATAM894 contains a clock module with 4 different internal oscillator types: two rc-oscillators, one 4-mhz crystal oscillator and one 32-khz crystal oscillator. the pins osc1 and osc2 are the interface to connect a crystal either to the 4-mhz, or to the 32-khz crystal oscillator. osc1 can be used as input for external clocks or to connect an external trimming resistor for the rc-oscillator 2. all necessary circuitry except the crys- tal and the trimming resistor is integrated on-chip. one of these oscillator types or an external input clock can be selected to generate the system clock (syscl). in applications that do not requ ire exact timing, it is possible to use the fully integrated rc-oscillator 1 without any external components. the rc-oscillator 1 center frequency tolerance is better than 50%. the rc-oscillator 2 is a trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor attached between osc1 and v dd . in this configuration, the rc-oscillator 2 frequency can be maintained stable to within a tolerance of 15% over the full operating temperature and voltage range. v dd low threshold middle threshold high threshold vms = 1 low threshold middle threshold high threshold vms = 0 3.0 v 2.6 v 2.2 v 1.3 v vmi vms = 1 vms = 0 positive slope negative slope vms = 1 vms = 0 interrupt negative slope interrupt positive slope internal reference level t
16 ATAM894 4679c?4bmcu?03/04 the clock module is programmable via software with the clock management register (cm) and the system configuration register (sc). the required oscillator configuration can be selected with the os1 bit and the os0 bit in the sc register. a programmable 4-bit divider stage allows the adjustment of the system clock speed. a special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the power-down mode. before the external clock is switched off, the internal rc-oscillator 1 must be selected with the ccs bit and then the sleep mode may be activated. in this state an interrupt can wake up the controller with the rc-oscil- lator, and the external oscillator can be activated and selected by software. a synchronization stage avoids clock periods that are too short if the clock source or the clock speed is changed. if an external input clock is selected, a supervisor circuit moni- tors the external input and generates a hardware reset if the external clock source fails or drops below 500 khz for more than 1 ms. figure 14. clock module the clock module generates two output clocks. one is the system clock (syscl) and the other the periphery (subcl). the syscl can supply the core and the peripherals and the subcl can supply only the peripherals with clocks. the modes for clock sources are programmable with the os1 bit and os0 bit in the sc register and the ccs bit in the cm register. ext. clock exin exout stop rc-oscillator 2 rcout2 stop r trim 4-mhz oscillator 4out stop oscin oscout oscin oscout 32-khz oscillator 32out oscin oscout rc- oscillator 1 rcout1 control stop in1 in2 cin /2 /2 /2 /2 divider sleep wdl osc-stop nstop ccs css1 css0 cm: bot - - - os1 os0 subcl syscl sc: * osc1 * osc2 * configurable cin/16 32 khz table 4. clock modes mode os1 os0 clock source for syscl clock source for subcl ccs = 1 ccs = 0 1 1 1 rc-oscillator 1 (intern) external input clock c in /16 2 0 1 rc-oscillator 1 (intern) rc-oscillator 2 with external trimming resistor c in /16 3 1 0 rc-oscillator 1 (intern) 4-mhz oscillator c in /16 4 0 0 rc-oscillator 1 (intern) 32-khz oscillator 32 khz
17 ATAM894 4679c?4bmcu?03/04 oscillator circuits and external clock input stage the ATAM894 series consists of four different internal oscillators: two rc-oscillators, one 4-mhz crystal oscillator, one 32-khz cryst al oscillator and one external clock input stage. rc-oscillator 1 fully integrated for timing insensitive applications, it is possible to use the fully integrated rc-oscillator 1. it operates without any external components and saves additional costs. the rc-oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. the basic center frequency of the rc-oscillator 1 is f o 4.0 mhz. the rc-oscillator 1 is selected by default after power-on reset. figure 15. rc-oscillator 1 external input clock the osc1 or osc2 can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. additionally, the external clock stage contains a supervisory circuit for the input clock. the supervisor function is con- trolled via the os1, os0 bit in the sc register and the ccs bit in the cm register. if the external input clock is missing for more than 1 ms and ccs = 0 is set in the cm register, the supervisory circuit generates a hardware reset. figure 16. external input clock rc-oscillator 1 rcout1 stop control rcout1 osc-stop table 5. supervisor function control bits os1 os0 ccs supervisor reset output (res) 110 enable 111 disable x 0 x disable ext. input clock exout stop ext. clock rcout1 osc-stop exin ccs res osc1 osc2 clock monitor ext. clock or
18 ATAM894 4679c?4bmcu?03/04 rc-oscillator 2 with external trimming resistor the rc-oscillator 2 is a high resolution tri mmable oscillator whereby the oscillator fre- quency can be trimmed with an external resistor between osc1 and v dd . in this configuration, the rc-oscillator 2 frequency can be maintained stable with a tolerance of 15% over the full operating temperature and a voltage range v dd from 2.5 v to 6.0 v. for example: an output frequency at the rc-oscillator 2 of 2 mhz can be obtained by connecting a resistor r ext =360k ? (see figure 17). figure 17. rc-oscillator 2 4-mhz oscillator the ATAM894 4-mhz oscillator options need a crystal or ceramic resonator connected to the osc1 and osc2 pins to establish oscillation. all the necessary oscillator circuitry, with the exception of the actual crystal, resonator, c 3 and c 4 are integrated on-chip. figure 18. 4-mhz crystal oscillator figure 19. ceramic resonator rc-oscillator 2 rcout2 stop rcout2 osc-stop r trim osc1 osc2 r ext v dd 4-mhz oscillator 4out 4out osc1 osc2 * oscin c 1 * c 2 oscout xtal 4 mhz * configurable stop osc-stop 4-mhz oscillator 4out stop 4out osc-stop osc1 osc2 * oscin c 1 * c 2 oscout cer. res * configurable c 3 c 4
19 ATAM894 4679c?4bmcu?03/04 32-khz oscillator some applications require long-term time keeping or low resolution timing. in this case, an on-chip, low power 32-khz crystal oscillator can be used to generate both the subcl and the syscl. in this mode, power consumption is greatly reduced. the 32-khz crystal oscillator can not be stopped while the power-down mode is in operation. figure 20. 32-khz crystal oscillator clock management the clock management register controls the system clock divider and synchronization stage. writing to this register triggers the synchronization cycle. clock management register (cm) 32-khz oscillator 32out 32out osc1 osc2 * oscin c 1 * c 2 oscout xtal 32 khz * configurable auxiliary register address: '3'hex bit 3bit 2bit 1bit 0 cm: nstop ccs css1 css0 reset value: 1111b nstop n ot stop peripheral clock nstop = 0, stops the peripheral clock while the core is in sleep mode nstop = 1, enables the peripheral clock while the core is in sleep mode ccs c ore c lock s elect ccs = 1, the internal rc-oscillator 1 generates syscl ccs = 0, the 4-mhz crystal oscillator, the 32-khz crystal oscillator, an external clock source or the rc-oscillator 2 with the external resistor at osc1 generates syscl dependent on the setting of os0 and os1 in the system configuration register css1 c ore s peed s elect 1 css0 c ore s peed s elect 0 table 6. core speed select css1 css0 divider note 0016 1 1 8 reset value 104 012
20 ATAM894 4679c?4bmcu?03/04 system configuration register (sc) note: if the bit ccs = 0 in the cm-register the rc-oscillator 1 always stops. primary register address: '3'hex bit 3 bit 2 bit 1 bit 0 sc: write bot ? os1 os0 reset value: 1x11b bot b rown- o ut t hreshold bot = 1, low brown-out voltage threshold (1.65 v) bot = 0, high brown-out voltage threshold (1.95 v) os1 o scillator s elect 1 os0 o scillator s elect 0 table 7. oscillator select mode os1 os0 input for subcl selected oscillators 111 c in /16 rc-oscillator 1 and external input clock 201 c in /16 rc-oscillator 1 and rc-oscillator 2 310 c in /16 rc-oscillator 1 and 4-mhz crystal oscillator 400 32 khz rc-oscillator 1 and 32-khz crystal oscillator
21 ATAM894 4679c?4bmcu?03/04 power-down modes the sleep mode is a shut-down condition wh ich is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. in this mode, the system clock is stopped. the sleep mode is entered via the sleep instruc- tion. this instruction sets the interrupt enabl e bit (i) in the condition code register to enable all interrupts and stops the core. during the sleep mode the peripheral modules remain active and are able to generate interrupts. the microcontroller exits the sleep mode by carrying out any interrupt or a reset. the sleep mode can only be kept when none of the interrupt pending or active register bits are set. the application of the $autosleep routine ensures the correct function of the sleep mode. for standard applications use the $autosleep routine to enter the power-down mode. using the sleep instruction instead of the $autosleep following an i/o instruction requires the insertion of 3 non-i/o instruction cycles (for example nop, nop, nop) between the in or out command and the sleep command. the total power consumption is directly proportional to the active time of the microcon- troller. for a rough estimation of the expected average system current consumption, the following formula should be used: i dd depends on v dd and f syscl the ATAM894 has various power-down modes. during the sleep mode the clock for the marc4 core is stopped. with the nstop bit in the clock management register (cm) it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. if the clock for the core and the peripherals is stopped the selected oscilla- tor is switched off. an exception is the 32-khz oscillator, if it is selected it runs continuously independent of the nstop bit. if the oscillator is stopped or the 32-khz oscillator is selected, power consumption is extremely low. table 8. power-down modes mode cpu core osc- stop (1) brown-out function rc-oscillator 1 rc-oscillator 2 4-mhz oscillator 32-khz oscillator external input clock active run no active run run yes power-down sleep no active run run yes sleep sleep yes stop stop run stop note: 1. osc-stop = sleep and nstop and wdl i total v dd ,f syscl () i sleep i dd t active t total ------------- - ?? ?? + =
22 ATAM894 4679c?4bmcu?03/04 peripheral modules addressing peripherals accessing the peripheral modules takes place via the i/o bus (see figure 21). the in or out instructions allow direct addressing of up to 16 i/o modules. a dual register addressing scheme has been adopted to enable direct addressing of the primary regis- ter. to address the auxiliary register, t he access must be switched with an auxiliary switching module. thus, a single in (or out) to the module address will read (or write into) the module primary register. accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. byte wide registers are accessed by multiple in- (or out-) instructions. for more complex peripheral modules, with a larger number of registers, extended address- ing is used. in this case a bank of up to 16 subport registers are indirectly addressed with the subport address. the first out-instruction writes the subport address to the subaddress register, the second in- or out-instruction reads data from or writes data to the addressed subport. figure 21. example of i/o addressing subaddress reg. subport fh i/o bus aux. reg. bank of primary regs. primary reg. (address pointer) auxiliary switch module indirect subport access to other modules 1 2 (subport register write) 3 4 5 1 2 3 6 6 4 5 example of qforth program code 1 2 4 5 3 6 addr. (asw) = auxililiary switch module address 1 2 2 1 2 2 4 5 5 (auxiliary register write) module asw module m1 module m2 module m3 subport eh primary reg. primary reg. subport 1 subport 0 dual register access single register access addr. (sport) addr. (m1) out sport_data addr. (m1) out (subport register read) addr. (sport) addr. (m1) out addr. (m1) in (subport register write byte) addr. (sport) addr. (m1) out sport_data (lo) addr. (m1) out sport_data (hi) addr. (m1) out (subport register read byte) addr. (sport) addr. (m1) out addr. (m1) in (hi) addr. (m1) in (lo) (primary register write) prim._data addr. (m2) out addr. (m2) addr. (asw) out aux._data addr. (m2) out (primary register read) addr. (m2) in (auxiliary register read ) addr. (m2) addr. (asw) out addr. (m2) in (auxiliary register write byte) addr. (m2) addr. (asw) out aux._data (lo) addr. (m2) out aux._data (hi) addr. (m2) out (primary register write) prim._data addr. (m3) out (primary register read) addr. (m3) in addr. (mx) = module mx address addr. (sport) = subport address prim._data = data to be written into primary register aux._data = data to be written into auxiliary register aux._data (lo) = data to be written into auxiliary register (low nibble) aux._data (hi) = data to be written into auxiliary register (high nibble) sport_data (lo) = data to be written into subport (low nibble) sport_data (hi) = data to be written into subport (high nibble) (lo) = sport_data (low nibble) (hi) = sport_data (high nibble)
23 ATAM894 4679c?4bmcu?03/04 table 9. peripheral addresses port address name write/read reset value register function module type see page 1 p1dat w/r 1xx1b port 1 - data register/input data m3 24 2 p2dat w/r 1111b port 2 - data register/pin data m2 26 auxiliary p2cr w 1111b port 2 - control register 26 3 sc w 1x11b system configuration register m3 20 cwd r xxxxb watchdog reset m3 13 auxiliary cm w 1111b clock management register m2 19 4 p4dat w/r 1111b port 4 - data register/pin data m2 29 auxiliary p4cr w 1111 1111b port 4 - control register (byte) 29 5 p5dat w/r 1111b port 5 - data register/pin data m2 28 auxiliary p5cr w 1111 1111b port 5 - control register (byte) 28 6 p6dat w/r 1xx1b port 6 - data register/pin data m2 30 auxiliary p6cr w 1111b port 6 - control register (byte) 30 7 t12sub w ? data to timer 1/2 subport m1 22 subport address 0 t2c w 0000b timer 2 control register m1 42 1 t2m1 w 1111b timer 2 mode register 1 m1 42 2 t2m2 w 1111b timer 2 mode register 2 m1 43 3 t2cm w 0000b timer 2 compare mode register m1 44 4 t2co1 w 1111b timer 2 compare register 1 m1 45 5 t2co2 w 1111 1111b timer 2 compare register 2 (byte) m1 45 6? ? ? reserved 7? ? ? reserved 8 t1c1 w 1111b timer 1 control register 1 m1 33 9 t1c2 w x111b timer 1 control register 2 m1 34 a wdc w 1111b watchdog control register m1 34 b-f reserved 8 asw w 1111b auxiliary/switch register asw 22 9 stb w xxxx xxxxb serial transmit buffer (byte) m2 69 srb r xxxx xxxxb serial receive buffer (byte) 69 auxiliary sic1 w 1111b serial inte rface control register 1 67 a sisc w/r 1x11b serial interface status/control register m2 68 auxiliary sic2 w 1111b serial inte rface control register 2 67 b t3sub w/r ? data to/from timer 3 subport m1 22 subport address 0 t3m w 1111b timer 3 mode register m1 54 1 t3cs w 1111b timer 3 clock select register m1 55 2 t3cm1 w 0000b timer 3 compare mode register 1 m1 56 3 t3cm2 w 0000b timer 3 compare mode register 2 m1 57 4 t3co1 w 1111 1111b timer 3 compare register 1 (byte) m1 57 4 t3cp r xxxx xxxxb timer 3 capture register (byte) m1 58 5 t3co2 w 1111 1111b timer 3 compare register 2 (byte) m1 57 6 w 1111b reserved 7-f ? reserved c t3c w 0000b timer 3 control register m3 55 t3st r x000b timer 3 status register m3 55 d, e --- ? reserved f vmc w 1111b voltage monitor control register m3 14 vmst r xx11b voltage monitor status register m3 14
24 ATAM894 4679c?4bmcu?03/04 bi-directional ports with the exception of port 1 and port 6, all other ports (2, 4 and 5) are 4 bits wide. port 1 and port 6 have a data width of 2 bits (bit 0 and bit 3). all ports may be used for data input or output. all ports are equipped with schmitt trigger inputs and a variety of mask options for open drain, open source, full complementary outputs, pull-up and pull-down transistors. all port data registers (pxdat) are i/o mapped to the primary address reg- ister of the respective port address and the port control register (pxcr), to the corresponding auxiliary register. there are five different directional ports available: port 1 2-bit wide bi-directional ports with automatic full bus width direction switching port 2 4-bit wide bit-wise-programmable i/o port port 5 4-bit wide bit-wise-programmable bi-directional port with optional strong pull-ups and programmable interrupt logic port 4 4-bit wide bit-wise-programmable bi-directional port also provides the i/o interface to timer 2, ssi, voltage monitor input and external interrupt input port 6 2-bit wide bit-wise-programmable bi-directional port also provides the i/o interface to timer 3 and external interrupt input bi-directional port 1 in port 1 the data direction register is not independently software programmable, the direction of the complete port being switched automatically when an i/o instruction occurs (see figure 22 on page 25). the port is switched to output mode via an out instruction and to input via an in instruction. the data written to a port will be stored into the output data latches and appears immediately at the port pin following the out instruction. after reset all output latches are set to '1' and the port is switched to input mode. an in instruction reads the condition of the associated pins. note: care must be taken when switching the bi-directional port from output to input. the capacitive pin loading at this port in conjunction with the high resistance pull-ups may cause the cpu to read the contents of the output data register rather than the external input state. to avoid this, one of the following programming techniques should be used: use two in-instructions and drop the first data nibble. the first in switches the port from output to input and the drop removes the first invalid nibble. the second in reads the valid pin state. use an out-instruction followed by an in-instruction. via the out-instruction, the capac- itive load is charged or discharged depending on the optional pull-up/pull-down configuration. write a '1' for pins with pull-up resistors and a '0' for pins with pull-down resistors.
25 ATAM894 4679c?4bmcu?03/04 figure 22. bi-directional port 1 bi-directional port 2 as all other bi-directional ports, this port includes a bit-wise-programmable control reg- ister (p2cr), which enables the individual programming of each port bit as input or output. it also opens up the possibility of reading the pin condition when in output mode. this is a useful feature for self testing and for serial bus applications. however, port 2 has an increased drive capability and an additional low resistance pull-up/-down transistor mask option. care should be taken connecting external components to bp20/nte. during any reset phase, the bp20/nte input is driven towards v dd by an additional internal strong pull-up transistor. this pin must not be pulled down (active or passive) to v ss during reset by any external circuitry representing a resistor of less than 150 k ? . this prevents the cir- cuit from unintended switching to test mode enable through the application circuitry at pin bp20/nte. resistors less than 150 k ? might lead to an undefined state of the inter- nal test logic, thus disabling the application firmware. to avoid any conflict with the optional internal pull-down transistors, bp20 handles the pull-down options in a different way than all other ports. bp20 is the only port that switches off the pull-down transistors during reset. figure 23. bi-directional port 2 out in reset i/o bus d r s q q nq r master reset p1daty (data out) (direction) bp1y switched switched (1) (1) mask options v dd static pull-up static pull-down pull-up pull-down (1) (1) (1) v dd master reset q q bp2y (1) mask options p2daty p2cry i/o bus d i/o bus i/o bus switched pull-up static pull-up (data out) (direction) s d (1) s static pull-down switched pull-down v dd v dd (1) (1) (1) (1) (1)
26 ATAM894 4679c?4bmcu?03/04 port 2 data register (p2dat) note: * bit 3 = msb, bit 0 = lsb port 2 control register (p2cr) note: value 1111b means all pins in input mode bi-directional port 5 as all other bi-directional ports, this port includes a bit-wise-programmable control reg- ister (p5cr), which allows the individual programming of each port bit as input or output. it also opens up the possibility of reading the pin condition when in output mode. this is a useful feature for self-testing and for serial bus applications. the port pins can also be used as external interrupt inputs (see figure 24 on page 27 and figure 25 on page 27). the interrupts (int1 and int6) can be masked or indepen- dently configured to trigger on either edge. the interrupt configuration and port direction is controlled by the port 5 control register (p5cr). an additional low resistance pull- up/-down transistor mask option provides an internal bus pull-up for serial bus applications. the port 5 data register (p5dat) is i/o mapped to the primary address register of address '5'h and the port 5 control register (p5cr) to the corresponding auxiliary reg- ister. the p5cr is a byte-wide register and is configured by writing first the low nibble and then the high nibble (see section ?addressing peripherals?). primary register address: '2'hex bit 3 * bit 2 bit 1 bit 0 p2dat p2dat3 p2dat2 p2dat1 p2dat0 reset value: 1111b auxiliary register address: '2'hex bit 3 bit 2 bit 1 bit 0 p2cr p2cr3 p2cr2 p2cr1 p2cr0 reset value: 1111b table 10. port 2 control register code 3 2 1 0 function x x x 1 bp20 in input mode x x x 0 bp20 in output mode x x 1 x bp21 in input mode x x 0 x bp21 in output mode x 1 x x bp22 in input mode x 0 x x bp22 in output mode 1 x x x bp23 in input mode 0 x x x bp23 in output mode
27 ATAM894 4679c?4bmcu?03/04 figure 24. bi-directional port 5 figure 25. port 5 external interrupts master reset q v dd bp5y (1) mask options p5daty i/o bus d in enable i/o bus (1) switched pull-up switched pull-down static pull-up (data out) s static pull-down v dd v dd (1) (1) (1) (1) (1) bidir. port data in in_enable bp53 p53m2 p53m1 p52m2 p52m1 p51m2 p51m1 p50m2 p50m1 decoder decoder decoder decoder bidir. port data in in_enable bp52 i/o-bus bidir. port data in in_enable bp51 i/o-bus bidir. port data in in_enable bp50 int1 int6 p5cr:
28 ATAM894 4679c?4bmcu?03/04 port 5 data register (p5dat) port 5 control register (p5cr) byte write p5xm2, p5xm1 ? port 5x interrupt mode/direction code bi-directional port 4 the bi-directional port 4 is a bit-wise configurable i/o port and provides the external pins for the timer 2, ssi and the voltage monitor input (vmi). as a normal port, it performs in exactly the same way as bi-directional port 2 (see figure 23 on page 25). two addi- tional multiplexes allow data and port direction control to be passed over to other internal modules (timer 2, vm or ssi). the i/o pins for the sc and sd lines have an additional mode to generate an ssi-interrupt. all four port 4 pins can be individually switched by the p4cr register. figure 26 on page 29 shows the internal interfaces to bi-directional port 4. primary register address: '5'hex bit 3 bit 2 bit 1 bit 0 p5dat p5dat3 p5dat2 p5dat1 p5dat0 reset value: 1111b auxiliary register address: '5'hex bit 3 bit 2 bit 1 bit 0 p5cr first write cycle p51m2 p51m1 p50m2 p50m1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p53m2 p53m1 p52m2 p52m1 reset value: 1111b table 11. port 5 control register auxiliary address: '5'hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp50 in input mode ? interrupt disabled x x 1 1 bp52 in input mode ? interrupt disabled x x 0 1 bp50 in input mode ? rising edge interrupt x x 0 1 bp52 in input mode ? rising edge interrupt x x 1 0 bp50 in input mode ? falling edge interrupt x x 1 0 bp52 in input mode ? falling edge interrupt x x 0 0 bp50 in output mode ? interrupt disabled x x 0 0 bp52 in output mode ? interrupt disabled 1 1 x x bp51 in input mode ? interrupt disabled 1 1 x x bp53 in input mode ? interrupt disabled 0 1 x x bp51 in input mode ? rising edge interrupt 0 1 x x bp53 in input mode ? rising edge interrupt 1 0 x x bp51 in input mode ? falling edge interrupt 1 0 x x bp53 in input mode ? falling edge interrupt 0 0 x x bp51 in output mode ? interrupt disabled 0 0 x x bp53 in output mode ? interrupt disabled
29 ATAM894 4679c?4bmcu?03/04 figure 26. bi-directional port 4 and port 6 port 4 data register (p4dat) port 4 control register (p4cr) byte write p4xm2, p4xm1 ? port 4x interrupt mode/direction code master reset q v dd bpxy (1) mask options pxdaty i/o bus d i/o bus i/o bus switched pull-up switched pull-down s pxcry s q d pxmry pout (direction) pdir intx (1) pin static pull-up static pull-down v dd v dd (1) (1) (1) (1) (1) primary register address: '4'hex bit 3bit 2bit 1bit 0 p4dat p4dat3 p4dat2 p4dat1 p4dat0 reset value: 1111b auxiliary register address: '4'hex bit 3 bit 2 bit 1 bit 0 p4cr first write cycle p41m2 p41m1 p40m2 p40m1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p43m2 p43m1 p42m2 p42m1 reset value: 1111b table 12. port 4 control register auxiliary address: '4'hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp40 in input mode x x 1 1 bp42 in input mode x x 1 0 bp40 in output mode x x 1 0 bp42 in output mode x x 0 1 bp40 enable alternate function (sc for ssi) x x 0 x bp42 enable alternate function (t2o for timer 2) x x 0 0 bp40 enable alternate function (falling edge interrupt input for int3) 1 1 x x bp43 in input mode 1 1 x x bp41 in input mode 1 0 x x bp43 in output mode 1 0 x x bp41 in output mode 0 1 x x bp43 enable alternate function (sd for ssi) 0 1 x x bp41 enable alternate function (vmi for voltage monitor input) 0 0 x x bp43 enable alternate function (falling edge interrupt input for int3) 0 0 x x bp41 enable alternate function (t2i external clock input for timer 2) ??
30 ATAM894 4679c?4bmcu?03/04 bi-directional port 6 the bi-directional port 6 is a bit-wise configurable i/o port and provides the external pins for the timer 3. as a normal port, it performs in exactly the same way as bi-directional port 6 (see figure 26 on page 29). two additional multiplexes allow data and port direc- tion control to be passed over to other internal modules (timer 3). the i/o pin for the t3i line has an additional mode to generate a timer 3-interrupt. all two port 6 pins can be individually switched by the p6cr register. figure 26 on page 29 shows the internal interfaces to bi-directional port 6. port 6 data register (p6dat) port 6 control register (p6cr) p6xm2, p6xm1 ? port 6x interrupt mode/direction code primary register address: '6'hex bit 3bit 2bit 1bit 0 p6dat p6dat3 - - p6dat0 reset value: 1xx1b auxiliary register address: '6'hex bit 3bit 2bit 1bit 0 p6cr p63m2 p63m1 p60m2 p60m0 reset value: 1111b table 13. port 6 control register auxiliary address: ?6?hex write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp60 in input mode 1 1 x x bp63 in input mode x x 1 0 bp60 in output mode 1 0 x x bp63 in output mode x x 0 x bp60 enable alternate port function (t3o for timer 3) 0 x x x bp63 enable alternate port function (t3i for timer 3)
31 ATAM894 4679c?4bmcu?03/04 universal timer/counter/ communication module (utcm) the universal timer/counter/communication module (utcm) consists of three timers (timer 1,timer 2, timer 3) and a synchronous serial interface (ssi). timer 1 is an interval timer that can be used to generate periodic interrupts and as prescaler for timer 2, timer 3, the serial interface and the watchdog function. timer 2 is an 8/12-bit timer with an external clock input (t2i) and an output (t2o). timer 3 is an 8-bit timer/counter with its own input (t3i) and output (t3o). the ssi operates as a two-wire serial interface or as shift register for modulation and demodulation. the modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. there is a multitude of modes in which the timers and the serial interface can work together. figure 27. utcm block diagram demodu- lator 3 8-bit counter 3 capture 3 compare 3/1 compare 3/2 modu- lator 3 mux mux control watchdog interval/prescaler timer 1 timer 3 modu- lator 2 4-bit counter 2/1 compare 2/1 mux mux dcg 8-bit counter 2/2 compare 2/2 control timer 2 mux 8-bit shift register receive buffer transmit buffer control ssi scl int4 int5 int2 nrst int3 pout tog2 tog3 t1out subcl syscl from clock module t3o t3i t2i t2o sc sd i/o bus
32 ATAM894 4679c?4bmcu?03/04 timer 1 the timer 1 is an interval timer which can be used to generate periodic interrupts and as prescaler for timer 2, timer 3, the serial interface and the watchdog function. the timer 1 consists of a programmable 14-stage divider that is driven by either subcl or syscl. the timer output signal can be used as prescaler clock or as subcl and as source for the timer 1 interrupt. because of other system requirements the timer 1 out- put t1out is synchronized with syscl. therefore, in the power-down mode sleep (cpu core sleep and osc-stop yes) the output t1out is stopped (t1out = 0). nevertheless, the timer 1 can be active in sleep and generate timer 1 interrupts. the interrupt is maskable via the t1im bit and the subcl can be bypassed via the t1bp bit of the t1c2 register. the time interval for the timer output can be programmed via the timer 1 control register t1c1. this timer starts running automatically after any power-on reset! if the watchdog func- tion is not activated, the timer can be restarted by writing into the t1c1 register with t1rm = 1. timer 1 can also be used as a watchdog timer to prevent a system from stalling. the watchdog timer is a 3-bit counter that is supplied by a separate output of timer 1. it gen- erates a system reset when the 3-bit counter overflows. to avoid this, the 3-bit counter must be reset before it overflows. the application software has to accomplish this by reading the cwd register. after power-on reset the watchdog must be activated by software in the $reset initial- ization routine. there are two watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is active and locked. this mode can only be stopped by carrying out a system reset. the watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog control register (wdc). figure 28. timer 1 module 14-bit prescaler cl1 4-bit watchdog mux wdcl t1im t1bp t1mux nrst int2 t1out t1cs syscl subcl
33 ATAM894 4679c?4bmcu?03/04 figure 29. timer 1 and watchdog timer 1 control register 1 (t1c1) note: * bit 3 = msb, bit 0 = lsb the three bits t1c[2:0] select the divider for timer 1. the resulting time interval depends on this divider and the timer 1 input clock source. the timer input can be supplied by the system clock, the 32-khz oscillator or via the clock management. if the clock manage- ment generates the subcl, the selected input clock from the rc-oscillator, 4-mhz oscillator or an external clock is divided by 16. q5 q1 q2 q3 q4 q6 q8 q8 q11 q11 q14 q14 res cl decoder watchdog mode control mux for interval timer decoder mux for watchdog timer t1rm t1c2 t1c1 t1c0 3 2 wdl wdr wdt1 wdt0 wdc res t1mux subcl t1bp t1im t1im=0 t1im=1 int2 t1out t1c2 reset (nrst) watchdog divider/8 divider reset t1c1 write of the t1c1 register cl1 wdcl read of the cwd register address: '7'hex ? subaddress: '8'hex bit 3* bit 2 bit 1 bit 0 t1c1 t1rm t1c2 t1c1 t1c0 reset value: 1111b t1rm t imer 1 r estart m ode t1rm = 0, write access without timer 1 restart t1rm = 1, write access with timer 1 restart note: if wdl = 0, timer 1 restart is impossible t1c2 t imer 1 c ontrol bit 2 t1c1 t imer 1 c ontrol bit 1 t1c0 t imer 1 c ontrol bit 0 table 14. timer 1 control bits t1c2 t1c1 t1c0 divider time interval with subcl time interval with subcl = 32 khz time interval with syscl = 2/1 mhz 0 0 0 2 subcl/2 61 s 1 s/2 s 0 0 1 4 subcl/4 122 s 2 s/4 s 0 1 0 8 subcl/8 244 s 4 s/8 s 0 1 1 16 subcl/16 488 s 8 s/16 s 1 0 0 32 subcl/32 0.977 ms 16 s/32 s 1 0 1 256 subcl/256 7.812 ms 128 s/256 s 1 1 0 2048 subcl/2048 62.5 ms 1024 s/2048 s 1 1 1 16384 subcl/16384 500 ms 8192 s/16384 s
34 ATAM894 4679c?4bmcu?03/04 timer 1 control register 2 (t1c2) note: 1. bit 3 = msb, bit 0 = lsb watchdog control register (wdc) note: 1. bit 3 = msb, bit 0 = lsb both these bits control the time interval for the watchdog reset. address: '7'hex ? subaddress: '9'hex bit 3 (1) bit 2bit 1bit 0 t1c2 ? t1bp t1cs t1im reset value: x111b t1bp t imer 1 subcl b y p assed t1bp = 1, tiout = t1mux t1bp = 0, t1out = subcl t1cs t imer 1 input c lock s elect t1cs = 1, cl1 = subcl (see figure 28 on page 32) t1cs = 0, cl1 = syscl (see figure 28 on page 32) t1im t imer 1 i nterrupt m ask t1im = 1, disables timer 1 interrupt t1im = 0, enables timer 1 interrupt address: '7'hex ? subaddress: 'a'hex bit 3 (1) bit 2bit 1bit 0 wdc wdl wdr wdt1 wdt0 reset value: 1111b wdl w atch d og l ock mode wdl = 1, the watchdog can be enabled and disabled by using the wdr bit wdl = 0, the watchdog is enabled and locked. in this mode the wdr bit has no effect. after the wdl bit is cleared, the watchdog is active until a system reset or power-on reset occurs wdr w atch d og r un and stop mode wdr = 1, the watchdog is stopped/disabled wdr = 0, the watchdog is active/enabled wdt1 w atch d og t ime 1 wdt0 w atch d og t ime 0 table 15. watchdog time control bits wdt1 wdt0 divider delay time to reset with t in = 1/32 khz delay time to reset with t in = 1/(2/1 mhz) 0 0 512 15.625 ms 0.256 ms/0.512 ms 0 1 2048 62.5 ms 1.024 ms/2.048 ms 1 0 16384 0.5 s 8.2 ms/16.4 ms 1 1 131072 4 s 65.5 ms/131 ms
35 ATAM894 4679c?4bmcu?03/04 timer 2 features 8/12-bit timer for interrupt, square-wave, pulse and duty cycle generation baud-rate generation for the internal shift register manchester and bi-phase modulation together with the ssi carrier frequency generation and modulation together with the ssi timer 2 can be used as interval timer for interrupt generation, as signal generator or as baud-rate generator and modulator for the serial interface. it consists of a 4-bit and an 8-bit up counter stage which both have comp are registers. the 4-bit counter stages of timer 2 are cascadable as an 12-bit timer or as an 8-bit timer with a 4-bit prescaler. the timer can also be configured as an 8-bit timer and separate a 4-bit prescaler. the timer 2 input can be supplied via the syst em clock, the external input clock (t2i), the timer 1 output clock or the shift clock of the serial interface. the external input clock t2i is not synchronized with syscl. therefore, it is possible to use timer 2 with a higher clock speed than syscl. furthermore, with that input clock the timer 2 operates in the power-down mode sleep (cpu core sleep and osc-stop yes) as well as in power-down (cpu core sleep and osc-stop no). all other clock sources supply no clock signal in sleep if nstop = 0. the 4-bit counter stages of timer 2 have an additional clock output (pout). its output has a modulator stage that allows the generation of pulses as well as the gen- eration and modulation of carrier frequencies. the timer 2 output can modulate with the shift register data output to generate bi-phase- or manchester code. if the serial interface is used to modulate a bit-stream, the 4-bit stage of timer 2 has a special task. the shift register can only handle bit-stream lengths divisible by 8. for other lengths, the 4-bit counter stage can be used to stop the modulator after the right bit-count is shifted out. if the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier fre- quency and duty cycle. the 8-bit counter is used to enable and disable the modulator output for a programmable count of pulses. for programming the time interval, the timer has a 4-bit and an 8-bit compare register. for programming the timer function, it has four mode and control registers. the compar- ator output of stage 2 is controlled by a special compare mode register (t2cm). this register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match ev ent or the counter overflow. this archi- tecture enables the timer function for various modes. the timer 2 has a 4-bit compare register (t2co1) and an 8-bit compare register (t2co2). both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. for 12-bit compare data value: m = x +1 0 x 4095 for 8-bit compare data value: n = y + 1 0 y 255 for 4-bit compare data value: l = z +1 0 z 15
36 ATAM894 4679c?4bmcu?03/04 figure 30. timer 2 timer 2 modes mode 1: 12-bit compare counter the 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. a com- pare match signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. the compare action is programmable via the compare mode register (t2cm). the 4-bit counter overflow (ovf1) supplies the clock output (pout) with clocks. the duty cycle generator (dcg) has to be bypassed in this mode. figure 31. 12-bit compare counter 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout ssi pout cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm control tog2 int4 bi-phase manchester modulator output mout m2 to modulator 3 t2o timer 2 modulator output-stage t2m2 so control ssi ssi i/o-bus t2c cl2/1 t2i syscl t1out tog3 scl i/o-bus dcgo 4-bit counter 4-bit compare res 4-bit register cm1 pout (cl2/1 /16) 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm-bit t2im t2ctm tog2 int4 cl2/1 dcg t2d1, 0
37 ATAM894 4679c?4bmcu?03/04 mode 2: 8-bit compare counter wi th 4-bit programmable prescaler the 4-bit stage is used as a programmable prescaler for the 8-bit counter stage. in this mode, a duty cycle stage is also available. this stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. the 4-bit compare output (cm1) supplies the clock output (pout) with clocks. figure 32. 8-bit compare counter mode 3/4: 8-bit compare counter and 4-bit programmable prescaler in these modes the 4-bit and the 8-bit c ounter stages work independently as a 4-bit prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. only in the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input (t2i) which is selected via the p4cr register. the 4-bit prescaler is started via activating of mode 3 and stopped and reset in mode 4. changing mode 3 and 4 has no effect for the 8-bit timer stage. the 4-bit stage can be used as prescaler for timer 3, the ssi or to generate the stop signal for modulator 2 and modulator 3. figure 33. 4-/8-bit compare counter 4-bit counter 4-bit compare res 4-bit register cm1 pout 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm-bit t2im t2ctm tog2 int4 cl2/1 dcg t2d1, 0 dcgo 4-bit counter 4-bit compare res 4-bit register 8-bit counter 8-bit compare 8-bit register ovf2 cm2 res t2rm t2otm timer 2 output mode and t2otm-bit t2im t2ctm tog2 int4 cl2/2 dcg t2d1, 0 dcgo p41m2, 1 p4cr cm1 pout cl2/1 mux tog3 t1out syscl scl t2cs1, 0 syscl t2i
38 ATAM894 4679c?4bmcu?03/04 timer 2 output modes the signal at the timer output is generated via modulator 2. in the toggle mode, the com- pare match event toggles the output t2o. for high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. in the duty-cycle burst modulator modes the dcg output is connected to t2o and switched on and off either by the toggle flip- flop output or the serial data line of the ssi. modulator 2 also has 2 modes to output the content of the serial interface as bi-phase or manchester code. the modulator output stage can be configured by the output control bits in the t2m2 register. the modulator is started with the start of the shift register (sir = 0) and stopped either by carrying out a shift register stop (sir = 1) or compare match event of stage 1 (cm1) of timer 2. for this task, timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (scl). figure 34. timer 2 modulator output stage timer 2 output signals timer 2 output mode 1 toggle mode a: a timer 2 compare match toggles the output flip-flop (m2) t2o figure 35. interrupt timer/square wave generator ? the output toggles with each edge compare match event toggle res/set bi-phase/ manchester modulator t2top t2os2, 1, 0 t2m2 t2o m2 m2 s1 s2 s3 modulator 3 re fe omsk ssi control tog2 so dcgo 4 000123 4 0123 4 0123 01 input counter 2 t2r counter 2 cmx int4 t2o
39 ATAM894 4679c?4bmcu?03/04 toggle mode b: a timer 2 compare match toggles the output flip-flop (m2) t2o figure 36. pulse generator ? the timer output toggles with the timer start if the t2ts bit is set toggle mode c : a timer 2 compare match toggles the output flip-flop (m2) t2o figure 37. pulse generator ? the timer toggles with timer overflow and compare match 4 000123 567 4 0123 56 input counter 2 t2r counter 2 cmx int4 t2o toggle by start t2o 4095/ 255 4 000123 567 4 0123 56 input counter 2 t2r counter 2 cmx ovf2 int4 t2o 4095/ 255
40 ATAM894 4679c?4bmcu?03/04 timer 2 output mode 2 duty cycle burst generator 1: the dcg output signal (dcgo) is given to the output, and gated by the output flip-flop (m2) figure 38. carrier frequency burst modulation with timer 2 toggle flip-flop output timer 2 output mode 3 duty cycle burst generator 2: the dcg output signal (dcgo) is given to the output, and gated by the ssi internal data output (so) figure 39. carrier frequency burst modulation with the ssi data output timer 2 output mode 4 bi-phase modulator: timer 2 modulates the ssi internal data output (so) to bi-phase code. figure 40. bi-phase modulation 1 20120123450120123456780123456789 10 012345 dcgo counter 2 tog2 m2 t2o counter = compare register (= 2) 1 201201201201201201201201201201201201201 dcgo counter 2 tog2 so t2o counter = compare register (= 2) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 tog2 sc so t2o 000 0 00110101 11 1 1 8-bit sr data bit 7 bit 0 data: 00110101
41 ATAM894 4679c?4bmcu?03/04 timer 2 output mode 5 manchester modulator: timer 2 modulates the ssi internal data output (so) to manchester code figure 41. manchester modulation timer 2 output mode 7 pwm mode: pulse-width modulation output on timer 2 output pin (t2o) in this mode the timer overflow defines the period and the compare register defines the duty-cycle. during one period only the first compare match occurrence is used to toggle the timer output flip-flop. until the overflow all further compare match are ignored. this avoids the situation that changing the compare register causes the occurrence of sev- eral compare match during one period. the resolution at the pulse-width modulation timer 2 mode 1 is 12-bit and all other timer 2 modes are 8-bit. figure 42. pwm modulation tog2 sc so t2o 00 0 0011 0101 11 1 1 8-bit sr data bit 7 bit 0 0 bit 7 bit 0 data: 00110101 0 0 50 255 100 0 255 0 150 255 0 50 255 0 100 t2r input clock counter 2/2 counter 2/2 ovf2 cm2 int4 t2o load the next compare value t2co2 = 150 load load t1 t2 t3 t1 t2 tt t t t
42 ATAM894 4679c?4bmcu?03/04 timer 2 registers timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. all registers are indirectly addressed using extended addressing as described in section ?addressing peripherals?. the alternate functions of the ports bp41 or bp42 must be selected with the port 4 control register p4cr, if one of the timer 2 modes require an input at t2i/bp41 or an output at t2o/bp42. timer 2 control register (t2c) timer 2 mode register 1 (t2m1) address: '7'hex ? subaddress: '0'hex bit 3 bit 2 bit 1 bit 0 t2c t2cs1 t2cs0 t2ts t2r reset value: 0000b t2cs1 t imer 2 c lock s elect bit 1 t2cs0 t imer 2 c lock s elect bit 0 t2ts t imer 2 t oggle with s tart t2ts = 0, the output flip-flop of timer 2 is not toggled with the timer start t2ts = 1, the output flip-flop of timer 2 is toggled when the timer is started with t2r t2r t imer 2 r un t2r = 0, timer 2 stop and reset t2r = 1, timer 2 run table 16. timer 2 clock select bits t2cs1 t2cs0 input clock (cl 2/1) of counter stage 2/1 0 0 system clock (syscl) 0 1 output signal of timer 1 (t1out) 1 0 internal shift clock of ssi (scl) 11reserved address: '7'hex ? subaddress: '1'hex bit 3 bit 2 bit 1 bit 0 t2m1 t2d1 t2d0 t2ms1 t2ms0 reset value: 1111b t2d1 t imer 2 d uty cycle bit 1 t2d0 t imer 2 d uty cycle bit 0 t2ms1 t imer 2 m ode s elect bit 1 t2ms0 t imer 2 m ode s elect bit 0 table 17. timer 2 duty cycle bits t2d1 t2d0 function of duty cycle gene rator (dcg) additional divider effect 1 1 bypassed (dcgo0) /1 1 0 duty cycle 1/1 (dcgo1) /2 0 1 duty cycle 1/2 (dcgo2) /3 0 0 duty cycle 1/3 (dcg03) /4
43 ATAM894 4679c?4bmcu?03/04 duty cycle generator the duty cycle generator generates duty cycles of 25%, 33% or 50%. the frequency at the duty cycle generator output depends on the duty cycle and the timer 2 prescaler setting. the dcg-stage can also be used as an additional programmable prescaler for timer 2. figure 43. dcg output signals timer 2 mode register 2 (t2m2) table 18. timer 2 mode select bits mode t2ms1 t2ms0 clock output (pout) timer 2 modes 1 1 1 4-bit counter overflow (ovf1) 12-bit compare counter, the dcg have to be bypassed in this mode 2 1 0 4-bit compare output (cm1) 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 3 0 1 4-bit compare output (cm1) 8-bit compare counter clocked by syscl or the external clock input t2i, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 4 0 0 4-bit compare output (cm1) 8-bit compare counter clocked by syscl or the external clock input t2i, 4-bit prescaler stop and resets dcgin dcgo0 dcgo1 dcgo2 dcgo3 address: '7'hex ? subaddress: '2'hex bit 3 bit 2 bit 1 bit 0 t2m2 t2top t2os2 t2os1 t2os0 reset value: 1111b t2top t imer 2 t oggle o utput p reset this bit allows the programmer to preset the timer 2 output t2o. t2top = 0, resets the toggle outputs with the write cycle (m2 = 0) t2top = 1, sets toggle outputs with the write cycle (m2 = 1) note: if t2r = 1, no output preset is possible t2os2 t imer 2 o utput s elect bit 2 t2os1 t imer 2 o utput s elect bit 1 t2os0 t imer 2 o utput s elect bit 0
44 ATAM894 4679c?4bmcu?03/04 if one of these output modes is used the t2o alternate function of port 4 must also be activated. timer 2 compare and compare mode registers timer 2 has two separate compare registers, t2co1 for the 4-bit stage and t2co2 for the 8-bit stage of timer 2. the timer compares the contents of the compare register cur- rent counter value and if it matches it generates an output signal. depending on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as ssi clock or as a clock for the next counter stage. in the 12-bit timer mode, t2co1 contains bits 0 to 3 and t2co2 bits 4 to 11 of the 12-bit compare value. in all other modes, the two compare registers work independently as a 4- and 8-bit compare register. when assigned to the compare register a compare event will be suppressed. table 19. timer 2 output select bits output mode t2os2 t2os1 t2os0 clock output 1111 toggle mode: a timer 2 compare match toggles the output flip-flop (m2) t2o 2110 duty cycle burst generator 1: the dcg output signal (dcg0) is given to the output and gated by the output flip-flop (m2) 3101 duty cycle burst generator 2: the dcg output signal (dcgo) is given to the output and gated by the ssi internal data output (so) 4100 bi-phase modulator: timer 2 modulates the ssi internal data output (so) to bi-phase code 5011 manchester modulator: timer 2 modulates the ssi internal data output (so) to manchester code 6010 ssi output: t2o is used directly as ssi internal data output (so) 7 0 0 1 pwm mode: an 8/12-bit pwm mode 8000not allowed
45 ATAM894 4679c?4bmcu?03/04 timer 2 compare mode register (t2cm) timer 2 compare register 1 (t2co1) in prescaler mode the clock is bypassed if the compare register t2co1 contains 0. timer 2 compare register 2 (t2co2) byte write address: '7'hex ? subaddress: '3'hex bit 3bit 2bit 1bit 0 t2cm t2otm t2ctm t2rm t2im reset value: 0000b t2otm t imer 2 o verflow t oggle m ask bit t2otm = 0, disable overflow toggle t2otm = 1, enable overflow toggle, a counter overflow (ovf2) toggles output flip-flop (tog2). if the t2otm bit is set, only a counter overflow can generate an interrupt except on the timer 2 output mode 7 t2ctm t imer 2 c ompare t oggle m ask bit t2ctm = 0, disable compare toggle t2ctm = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (tog2). in timer 2 output mode 7 and when the t2ctm bit is set, only a match of the counter with the compare register can generate an interrupt t2rm t imer 2 r eset m ask bit t2rm = 0, disable counter reset t2rm = 1, enable counter reset, a match of the counter with the compare register resets the counter t2im t imer 2 i nterrupt m ask bit t2im = 0, disable timer 2 interrupt t2im = 1, enable timer 2 interrupt table 20. timer 2 toggle mask bits timer 2 output mode t2otm t2ctm timer 2 interrupt source 1, 2, 3, 4, 5 and 6 0 x compare match (cm2) 1, 2, 3, 4, 5 and 6 1 x overflow (ovf2) 7 x 1 compare match (cm2) address: '7'hex ? subaddress: '4'hex t2co1 write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b address: '7?hex ? subaddress: '5'hex t2co2 first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b
46 ATAM894 4679c?4bmcu?03/04 timer 3 features two compare registers capture register edge sensitive input with zero cross detection capability trigger and single action modes output control modes automatic modulation and demodulation modes fsk modulation pulse width modulation (pwm) manchester demodulation together with ssi bi-phase demodulation together with ssi pulse-width demodulation together with ssi figure 44. timer 3 timer 3 consists of an 8-bit up-counter with two compare registers and one capture reg- ister. the timer can be used as event counter, timer and signal generator. its output can be programmed as modulator and demodulator for the serial interface. the two com- pare registers enable various modes of signal generation, modulation and demodulation. the counter can be driven by internal and external clock sources. for external clock sources, it has a programmable edge-sensitive input which can be used as counter input, capture signal input or trig ger input. this timer input is synchronized with syscl. therefore, in the power-down mode sleep (cpu core sleep and osc- stop yes), this timer input is stopped too. the counter is readable via its capture regis- ter while it is running. in capture mode, the counter value can be captured by a programmable capture event from the timer 3 input or timer 2 output. 8-bit counter 3 res compare 3/1 t3co1 t3cp t3co2 control t3o cl3 t3i t3ex syscl t1out pout i/o-bus compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu- lator 3 m2 control so tog3 int5 res cm31 t3i t3ex tog2 si sci t3m t3cs i/o-bus timer 2 ssi ssi cp3
47 ATAM894 4679c?4bmcu?03/04 a special feature of this timer is the trigger- and single-action mode. in trigger mode, the counter starts counting triggered by the external signal at its input. in single-action mode, the counter counts only one time up to the programmed compare match event. these modes are very useful for modulation, demodulation, signal generation, signal measurement and phase control. for phase control, the timer input is protected against negative voltages and has zero-cross detection capability. timer 3 has a modulator output stage and input functions for demodulation. as modula- tor it works together with timer 2 or the serial interface. when the shift register is used for modulation the data shifted out of the register is encoded bit-wise. in all demodula- tion modes, the decoded data bits are shifted automatically into the shift register. figure 45. counter 3 stage timer/counter modes timer 3 has 6 timer modes and 6 modulator/demodulator modes. the mode is set via the timer 3 mode register t3m. in all these modes, the compare register and the compare-mode register belonging to it define the counter value for a compare match and the action of a compare match. a match of the current counter value with the content of one compare register triggers a counter reset, a timer 3 interrupt or the toggling of the output flip-flop. the compare mode registers t3m1 and t3m2 contain the mask bits for enabling or disabling these actions. the counter can also be enabled to execute single actions with one or both compare registers. if this mode is set the corresponding compare match event is generated only once after the counter starts. most of the timer modes use their compare registers alternately. after the start has been activated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third is carried out again via the compare reg- ister 1 and so on. this makes it easy to generate signals with constant periods and variable duty cycle or to generate signals with variable pulse and space widths. 8-bit comparator compare register 1 res capture register 8-bit counter compare register 2 control c31 c32 control t3sm1 nq d t3rm1 t3im1 t3tm1 tog2 t3i t3tm2 t3im2 t3rm2 t3sm2 nq d cl3 t3eim tog3 int5 cm31 cm32 : t3m1 : t3m2
48 ATAM894 4679c?4bmcu?03/04 if single-action mode is set for one compare register, the comparison is always carried out after the first cycle via the other compare register. the counter can be started and stopped via the control register t3c. this register also controls the initial level of the output before start. t3c contains the interrupt mask for a t3i input interrupt. via the timer 3 clock-select register, the internal or external clock source can be selected. this register selects also the active edge of the external input. an edge at the external input t3i can generate also an interrupt if the t3eim bit is set and the timer 3 is stopped (t3r = 0) in the t3c register. the status of the timer as well as the occurrence of a compare match or an edge detect of the input signal is indicated by the status register t2st. this allows identification of the interrupt source because all these events share only one timer interrupt. timer 3 compares data values. the timer 3 has two 8-bit compare registers (t3co1, t3co2). the compare data value can be ?m? for each of the timer 3 compare registers. the compare data value for the compare registers is: m = x +1 0 x 255 timer 3 ? mode 1: timer/counter the selected clock from an internal or external source increments the 8-bit counter. in this mode, the timer can be used as event counter for external clocks at t3i or as timer for generating interrupts and pulses at t3o. the counter value can be read by the soft- ware via the capture register. figure 46. counter reset with each compare match 0 000123 5 1234 0 0123 12 t3r counter 3 cm31 int5 t3o 3 cm32
49 ATAM894 4679c?4bmcu?03/04 figure 47. counter reset with compare register 2 and toggle with start figure 48. single action of compare register 1 timer 3 ? mode 2: timer/counter, external trigger restart and external capture (with t3i input) the counter is driven by an internal clock source. after starting with t3r, the first edge from the external input t3i starts the counter. the following edges at t3i load the cur- rent counter value into the capture register, resets the counter and restarts it. the edge can be selected by the programmable edge decoder of the timer input stage. if single- action mode is activated for one or both compare registers the trigger signal restarts the single action. figure 49. externally triggered counter reset and start combined with single-action mode 4 000123 567 4 0123 56 t3r counter 3 cm31 int5 t3o toggle by start t3o 89 cl3 cm32 0 0123456789 10 012 counter 3 cm31 cm32 t3o 012012012012012012012 01201 toggle by start t3r 00000000123456 counter 3 t3ex cm31 cm32 78910012xxx012345678910 012xx t3r xx t3o
50 ATAM894 4679c?4bmcu?03/04 timer 3 ? mode 3: timer/counter, internal trigger restart and internal capture (with tog2) the counter is driven by an internal or external (t3i) clock source. the output toggle sig- nal of timer 2 resets the counter. the counter value before the reset is saved in the capture register. if single-action mode is activated for one or both compare registers, the trigger signal restarts the single actions. this mode can be used for frequency measure- ments or as event counter with time gate (see section ?combination mode 10?). figure 50. event counter with time gate timer 3 - mode 4: timer/counter the timer runs as timer/counter in mode 1, but its output t3o is used as output for the timer 2 output signal. timer 3 ? mode 5: timer/counter, external trigger restart and external capture (with t3i input) the timer 3 runs as timer/counter in mode 2, but its output t3o is used as output for the timer 2 output signal. timer 3 modulator/demodulator modes timer 3 ? mode 6: carrier frequency bu rst modulation controlled by timer 2 output toggle flip?flop (m2) the timer 3 counter is driven by an internal or external clock source. its compare- and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. the output toggle flip-flop of timer 2 is used to enable or disable the timer 3 output. timer 2 can be driven by the toggle output signal of timer 3 or any other clock source (see section ?combination mode 11?). timer 3 ? mode 7: carrier frequency burst modulation controlled by ssi internal output (so) the timer 3 counter is driven by an internal or external clock source. its compare- and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. the output (so) of the ssi is used to enable or disable the timer 3 output. the ssi should be supplied with the toggle signal of timer 2 (see section ?combination mode 12?). 0 01 2 3 4567 8 910 counter 3 tog2 t3cp- register 11 01 2 40 1 t3i 2 3 t3r capture value = 0 capture value = 11 capture value = 4
51 ATAM894 4679c?4bmcu?03/04 timer 3 ? mode 8: fsk modulation with shift register data (so) the two compare registers are used for generating two different time intervals. the ssi internal data output (so) selects which compare register is used for the output fre- quency generation. a '0' level at the ssi data output enables the compare register 1. a '1' level enables compare register 2. the compare- and compare mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. the ssi can be supplied with the toggle signal of timer 2. the timer 3 counter is driven by an internal or external clock source. the timer 2 counter is driven by the counter 3 (tog3) (see section ?combination mode 13?). figure 51. fsk modulation timer 3 ? mode 9: pulse-width modulation with the shift register the two compare registers are used for generating two different time intervals. the ssi internal data output (so) selects which compare register is used for the output pulse generation. in this mode both compare- and compare mode registers must be pro- grammed for generating the two pulse widths. it is also useful to enable the single-action mode for extreme duty-cycles. timer 2 is used as baud-rate generator and for the trig- ger restart of timer 3. the ssi must be supplied with a toggle signal of timer 2. the counter is driven by an internal or external clock source (see section ?combination mode 7?). figure 52. pulse-width modulation 01234012340123 counter 3 cm31 cm32 so 401201201201201201201 20123 t3r 40 t3o 1 01 0 000000000 0000 counter 3 cm31 cm32 t3o 00000123456789 101112 13 1415 0 12345 tog2 67 8 1 9 11 12 10 14 13 0 2 3 14 15 0 0 0 1 sir so sco t3r
52 ATAM894 4679c?4bmcu?03/04 timer 3 ? mode 10: manchester dem odulation/ pulse-width demodulation for manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. these edges are evaluated by the demodulator stage. the timer stage is used to generate the shift clock for the ssi. the compare register 1 match event defines the correct moment for shifting the state from the input t3i as the decoded bit into shift register - after that the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. the compare register 2 can also be used to detect a time-out error and handle it with an interrupt routine (see section ?combination mode 8?). figure 53. manchester demodulation timer 3 ? mode 11: bi-phase demodulation in the bi-phase demodulation mode, the timer operates like in manchester demodulation mode. the difference is that the bits are decoded via a toggle flip-flop. this flip-flop sam- ples the edge in the middle of the bit-frame and the compare register 1 match event shifts the toggle flip-flop output into a shift register (see section ?combination mode 9?). figure 54. bi-phase demodulation 1011100 110 11 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 synchronize manchester demodulation mode timer 3 mode t3ex si sr-data t3i cm31 = sci 100110 011 1 1 01 bit 7bit 6bit 5bit 4bit 3bit 2bit 1 synchronize bi-phase demodulation mode timer 3 mode t3ex q1 = si cm31 = sci sr-data 0000 t3i reset counter 3 101010 bit 0
53 ATAM894 4679c?4bmcu?03/04 timer 3 ? mode 12: timer/counter wi th external capture mode (t3i) the counter is driven by an internal clock source and an edge at the external input t3i loads the counter value into the capture register. the edge can be selected with the pro- grammable edge detector of the timer input stage. this mode can be used for signal and pulse measurements. figure 55. external capture mode timer 3 modulator for carrier frequency burst modulation if the output stage operates as pulse-width modulator for the shift register the output can be stopped with stage 1 of timer 2. for this task, the timer mode 3 must be used and the prescaler must be supplied by the internal shift clock of the shift register. the modulator can be started with the start of the shift register (sir = 0) and stopped either by a shift register stop (sir = 1) or compare match event of stage 1 of timer 2. for this task, the timer 2 must be used in mode 3 and the prescaler stage must be sup- plied by the internal shift clock of the shift register. figure 56. modulator 3 timer 3 demodulator for bi-phase, manchester and pulse-width-modulated signals the demodulator stage of timer 3 can be used to decode bi-phase, manchester and pulse-width-coded signals figure 57. timer 3 demodulator 3 0123456789 1011 counter 3 t3cp- register 15 t3i t3r capture value = x capture value = 17 capture value = 35 0 12 13 14 16 20 17 18 19 22 21 23 27 24 2526 29 28 30 34 31 32 33 36 35 37 41 3839 40 t3 set res t3o t3top omsk tog3 so ssi/ control m2 m3 mux t3m 0 1 2 3 timer 3 mode t3o 6 mux 1 7 mux 2 9 mux 3 other mux 0 demodulator 3 t3ex res cm31 counter 3 reset counter 3 control sci si t3i t3m
54 ATAM894 4679c?4bmcu?03/04 timer 3 registers timer 3 mode register (t3m) note: 1. in this mode, the ssi can be used only as demodulator (8-bit nrz rising edge). all other ssi modes are not allowed. address: 'b'hex ? subaddress: '0'hex bit 3bit 2bit 1bit 0 t3m3 t3m2 t3m1 t3m0 reset value: 1111b t3m3 t imer 3 m ode select bit 3 t3m2 t imer 3 m ode select bit 2 t3m1 t imer 3 m ode select bit 1 t3m0 t imer 3 m ode select bit 0 table 21. timer 3 mode select bits mode t3m3 t3m2 t3m1 t3m0 timer 3 modes 11111timer/counter with a read access 21110 timer/counter, external capture and external trigger restart mode (t3i) 31101 timer/counter, internal capture and internal trigger restart mode (tog2) 41100timer/counter mode 1 without output (t2o -> t3o) 51011timer/counter mode 2 without output (t2o -> t3o) 61010burst modulation with timer 2 (m2) 71001burst modulation with shift register (so) 81000fsk modulation with shift register (so) 90111 pulse-width modulation with shift register (so) and timer 2 (tog2), internal trigger restart (sco) -> counter reset 100110 manchester demodulation/pulse-width demodulation (1) (t2o -> t3o) 110101biphase demodulation (t2o -> t3o) 120100timer/counter with external capture mode (t3i) 130011not allowed 140010not allowed 150001not allowed 160000not allowed
55 ATAM894 4679c?4bmcu?03/04 timer 3 control register 1 (t3c) write timer 3 status register 1 (t3st) read note: the status bits t3c1, t3c2 and t3ed will be reset after a read access to t3st. timer 3 clock select register (t3cs) primary register address: 'c'hex ? write bit 3bit 2bit 1bit 0 write t3eim t3top t3ts t3r reset value: 0000b t3eim t imer 3 e dge i nterrupt m ask t3eim = 0, disables the interrupt when an edge event for timer 3 occurs (t3i) t3eim = 1, enables the interrupt when an edge event for timer 3 occurs (t3i) t3top t imer 3 t oggle o utput p reset t3top = 0, sets toggle output (m3) to '0' t3top = 1, sets toggle output (m3) to '1' note: if t3r = 1, no output preset is possible t3ts t imer 3 t oggle with s tart t3ts = 0, timer 3 output is not toggled during the start t3ts = 1, timer 3 output is toggled if started with t3r t3r t imer 3 r un t3r = 0, timer 3 stop and reset t3r = 1, timer 3 run primary register address: 'c'hex ? read bit 3bit 2bit 1bit 0 read - - - t3ed t3c2 t3c1 reset value: x000b t3ed t imer 3 e dge d etect this bit will be set by the edge-detect logic of timer 3 input (t3i) t3c2 t imer 3 c ompare 2 this bit will be set when a match occurs between counter 3 and t3co2 t3c1 t imer 3 c ompare 1 this bit will be set when a match occurs between counter 3 and t3co1 address: 'b'hex ? subaddress: '1'hex bit 3 bit 2 bit 1 bit 0 t3cs t3e1 t3e0 t3cs1 t3cs0 reset value: 1111b t3e1 t imer 3 e dge select bit 1 t3e0 t imer 3 e dge select bit 0 table 22. timer 3 edge select bits t3e1 t3e0 timer 3 input edge select (t3i) 11 ? 10 positive edge at t3i pin 01 negative edge at t3i pin 00 each edge at t3i pin
56 ATAM894 4679c?4bmcu?03/04 timer 3 compare- and compare mode register timer 3 has two separate compare registers t3co1 and t3co2 for the 8-bit stage of timer 3. the timer compares the content of the compare register with the current counter value. if both match, it generates a signal. this signal can be used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as ssi clock or as clock for the next counter stage. for each compare register, a compare-mode reg- ister exists. these registers contain mask bits to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a compare match of the corresponding compare register. the mask bits for activating the single-action mode can also be located in the compare mode registers. when assigned to the com- pare register a compare event will be suppressed. timer 3 compare mode register 1 (t3cm1) t3cm1 contains the mask bits for the match event of the counter 3 compare register 1 t3cs1 t imer 3 c lock s ource select bit 1 t3cs0 t imer 3 c lock s ource select bit 0 table 23. timer 3 clock select bits t3cs1 tcs0 counter 3 input signal (cl3) 11 system clock (syscl) 10 output signal of timer 2 (pout) 01 output signal of timer 1 (t1out) 00 external input signal from t3i edge detect address: 'b'hex ? subaddress: '2'hex bit 3 bit 2 bit 1 bit 0 t3cm1 t3sm1 t3tm1 t3rm1 t3im1 reset value: 0000b t3sm1 t imer 3 s ingle action m ask bit 1 t3sm1 = 0, disables single-action compare mode t3sm1 = 1, enables single-compare mode. after this bit is set, the compare register (t3co1) is used until the next compare match t3tm1 t imer 3 compare t oggle action m ask bit 1 t3tm1 = 0, disables compare toggle t3tm1 = 1, enables compare toggle. a match of counter 3 with the compare register (t3co1) toggles the output flip-flop (tog3) t3rm1 t imer 3 r eset m ask bit 1 t3rm1 = 0, disables counter reset t3rm1 = 1, enables counter reset. a match of counter 3 with the compare register (t3co1) resets the counter 3 t3im1 t imer 3 i nterrupt m ask bit 1 t3rm1 = 0, disables timer 3 interrupt for t3co1 register. t3rm1 = 1, enables timer 3 interrupt for t3co1 register
57 ATAM894 4679c?4bmcu?03/04 timer 3 compare mode register 2 (t3cm2) t3cm2 contains the mask bits for the match event of counter 3 compare register 2 the compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program the output sig- nal. the single-action mask can also be used in this mode. it starts operating after the timer started with t3r. timer 3 compare register 1 (t3co1) byte write timer 3 compare register 2 (t3co2) byte write address: 'b'hex ? subaddress: '3'hex bit 3bit 2bit 1bit 0 t3cm2 t3sm2 t3tm2 t3rm2 t3im2 reset value: 0000b t3sm2 t imer 3 s ingle action m ask bit 2 t3sm2 = 0, disables single-action compare mode t3sm2 = 1, enables single-compare mode. after this bit is set, the compare register (t3co2) is used until the next compare match t3tm2 t imer 3 compare t oggle action m ask bit 2 t3tm2 = 0, disables compare toggle t3tm2 = 1, enables compare toggle. a match of counter 3 with the compare register (t3co2) toggles the output flip-flop (tog3) t3rm2 t imer 3 r eset m ask bit 2 t3rm2 = 0, disables counter reset t3rm2 = 1, enables counter reset. a match of counter 3 with the compare register (t3co2) resets the counter 3 t3im2 t imer 3 i nterrupt m ask bit 2 t3rm2 = 0, disables timer 3 interrupt for t3co2 register t3rm2 = 1, enables timer 3 interrupt for t3co2 register address: 'b'hex ? subaddress: '4'hex high nibble second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b low nibble first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b address: 'b'hex ? subaddress: '5'hex high nibble second write cycle bit 7 bit 6 bit 5 bit 4 reset value: 1111b low nibble first write cycle bit 3 bit 2 bit 1 bit 0 reset value: 1111b
58 ATAM894 4679c?4bmcu?03/04 timer 3 capture register the counter content can be read via the capture register. there are two ways to use the capture register. in modes 1 and 4, it is possible to read the current counter value directly out of the capture register. in the capture modes 2, 3, 5 and 12, a capture event like an edge at the timer 3 input or a signal from timer 2 stores the current counter value into the capture register. this counter value can be read from the capture register. timer 3 capture register (t3cp) byte read synchronous serial interface (ssi) ssi features 2- and 3-wire nrz 2-wire mode (mcl compatible), additional internal 2-wire link for multi-chip packaging solutions with timer 2 ? bi-phase modulation ? manchester modulation ? pulse-width demodulation ? burst modulation with timer 3 ? pulse-width modulation (pwm) ? fsk modulation ? bi-phase demodulation ? manchester demodulation ? pulse-width demodulation ? pulse position demodulation address: 'b'hex ? subaddress: ?4'hex high nibble first read cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb low nibble second read cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb
59 ATAM894 4679c?4bmcu?03/04 ssi peripheral configuration the synchronous serial interface (ssi) can be used either for serial communication with external devices such as eeproms, shift registers, display drivers, other microcontrol- lers, or as a means for generating and capturing on-chip serial streams of data. external data communication takes place via the port 4 (bp4), a multi-functional port which can be software configured by writing the appropriate control word into the p4cr register. the ssi can be configured in any of the following ways: 1. 2-wire external interface for bi-directional data communication with one data ter- minal and one shift clock. the ssi uses the port bp43 as a bi-directional serial data line (sd) and bp40 as shift clock line (sc). 2. 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (si), a serial output data terminal (so) and a shift clock (sc). the ssi uses bp40 as shift clock (sc), while the serial data input (si) is applied to bp43 (configured in p4cr as input!). serial output data (so) in this case is passed through to bp42 (configured in p4cr to t2o) via the timer 2 output stage (t2m2 configured in mode 6). 3. timer/ssi combined modes - the ssi used together with timer 2 or timer 3 is capable of performing a variety of data modulation and demodulation functions (see section ?timer?). the modulating data is converted by the ssi into a contin- uous serial stream of data which is in turn modulated in one of the timer functional blocks. serial demodulated data can be serially captured in the ssi and read by the controller. in the timer 3 modes 10 and 11 (demodulation modes) the ssi can only be used as demodulator. 4. multi-chip link (mcl) ? the ssi can also be used as an interchip data interface for use in single package multi-chip modules or hybrids. for such applications, the ssi is provided with two dedicated pads (mcl_sd and mcl_sc) which act as a two-wire chip-to-chip link. the mcl can be activated by the mcl control bit. should these mcl pads be used by the ssi, the standard sd and sc pins are not required and the corresponding port 4 ports are available as conventional data ports. figure 58. block diagram of the synchronous serial interface 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc sc control stb srb si timer 2/timer 3 output int3 sc i/o-bus i/o-bus ssi-control tog2 pout t1out syscl so si mcl_sc sd mcl_sd transmit buffer receive buffer sci /2
60 ATAM894 4679c?4bmcu?03/04 general ssi operation the ssi is comprised essentially of an 8-bit shift register with two associated 8-bit buff- ers the receive buffer (srb) for capturing the incoming serial data and a transmit buffer (stb) for intermediate storage of data to be serially output. both buffers are directly accessible by software. transferring the parallel buffer data into and out of the shift reg- ister is controlled automatically by the ssi control, so that both single byte transfers or continuous bit streams can be supported. the ssi can generate the shift clock (sc) either from one of several on-chip clock sources or accept an external clock. the external shift clock is output on, or applied to the port bp40. selection of an external clock source is performed by the serial clock direction control bit (scd). in the combinational modes, the required clock is selected by the corresponding timer mode. the ssi can operate in three data transfer modes - synchronous 8-bit shift mode, mcl compatible 9-bit shift modes or 8-bit pseudo mcl protocol (without acknowledge-bit). external ssi clocking is not supported in these modes. the ssi should thus generate and has full control over the shift clock so that it can always be regarded as an mcl bus master device. all directional control of the external data port used by the ssi is handled automatically and is dependent on the transmission direction set by the serial data direction (sdd) control bit. this control bit defines whether the ssi is currently operating in transmit (tx) mode or receive (rx) mode. serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. in the 9-bit mcl mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see section ?mcl protocol?). at the beginning of every telegram, the ssi control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. at the same time, incoming data is shifted into the shift register input. this incoming data is automatically loaded into the receive buffer when the complete telegram has been received. thus, data can be simultaneously received and transmitted if required. before data can be transferred, the ssi must first be activated. this is performed by means of the ssi reset control (sir) bit. all further operation then depends on the data directional mode (tx/rx) and the present status of the ssi buffer registers shown by the serial interface ready status flag (srdy). this srdy flag indicates the (empty/full) status of either the transmit buffer (in tx mode), or the receive buffer (in rx mode). the control logic ensures that data shif ting is temporarily halted at any time, if the appropriate receive/transmit buffer is no t ready (srdy = 0). the srdy status will then automatically be set back to ?1? and data shifting resumed as soon as the applica- tion software loads the new data into the transmit register (in tx mode) or frees the shift register by reading it into the receive buffer (in rx mode). another activity status (act) bit indicates the present status of the serial communica- tion. the act bit remains high for the duration of the serial telegram or if mcl stop or start conditions are currently being generated. both the current srdy and act status can be read in the ssi status register. to deactivate the ssi, the sir bit must be set high.
61 ATAM894 4679c?4bmcu?03/04 8-bit synchronous mode figure 59. 8-bit synchronous mode in the 8-bit synchronous mode, the ssi can operate as either a 2- or 3-wire interface (see section ?ssi peripheral configuration?). the serial data (sd) is received or trans- mitted in nrz format, synchronized to either the rising or falling edge of the shift clock (sc). the choice of clock edge is defined by the serial mode control bits (sm0,sm1). it should be noted that the transmission edge refers to the sc clock edge with which the sd changes. to avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. when used together with one of the timer modulator or demodulator stages, the ssi must be set in the 8-bit synchronous mode 1. in rx mode, as soon as the ssi is activated (sir = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. this first telegram is automati- cally transferred into the receive buffer and the srdy set to 0 indicating that the receive buffer contains valid data. at the same time an interrupt (if enabled) is generated. the ssi then continues shifting in the following 8-bit telegram. if, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer and the ssi will continue clocking in the next tele- gram. should, however, the first telegram not have been read (srdy = 1), then the ssi will stop, temporarily holding the second telegram in the shift register until a certain point of time when the controller is able to service the receive buffer. in this way no data is lost or overwritten. deactivating the ssi (sir = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. this can be used for clocking in a data telegram of less than 8 bits in length. care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivat- ing the ssi (sir = 1) and terminating the reception. after termination, the shift register contents will overwrite the receive buffer. sc sc data sd/to2 110 101 00 bit 7 bit 0 110 101 00 bit 7 bit 0 data: 00110101 (rising edge) (falling edge)
62 ATAM894 4679c?4bmcu?03/04 figure 60. example of an 8-bit synchronous transmit operation figure 61. example of an 8-bit synchronous receive operation 7654321 0 765432107654321 0 msb lsb tx data 1 tx data 2 tx data 3 msb lsb msb lsb write stb (tx data 2) write stb (tx data 3) write stb (tx data 1) sc sd sir srdy interrupt (ifn = 0) interrupt (ifn = 1) act 43210 76543210 msb lsb rx data 1 rx data 2 rx data 3 msb lsb msb lsb read srb (rx data 2) read srb (rx data 3) read srb (rx data 1) sc sd sir srdy interrupt (ifn = 0) interrupt (ifn = 1) act 765 43210 765 7654
63 ATAM894 4679c?4bmcu?03/04 9-bit shift mode in the 9-bit shift mode, the ssi is able to handle the mcl protocol (described below). it always operates as an mcl master device, i.e., sc is always generated and output by the ssi. both the mcl start and stop conditions are automatically generated whenever the ssi is activated or deactivated by the sir bit. in accordance with the mcl protocol, the output data is always changed in the clock low phase and shifted in on the high phase. before activating the ssi (sir = 0) and commencing an mcl dialog, the appropriate data direction for the first word must be set using the sdd control bit. the state of this bit controls the direction of the data port (bp43 or mcl_sd). once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift regis- ter. during the 9th clock period, the port direction is automatically switched over so that the corresponding acknowledge bit can be shifted out or read in. in transmit mode, the acknowledge bit received from the slave device is captured in the ssi status register (tack) where it can be read by the controller. in receive mode, the state of the acknowl- edge bit to be returned to the slave device is predetermined by the ssi status register (rack). changing the directional mode (tx/rx) should not be performed during the transfer of an mcl telegram. one should wait until the end of the telegram which can be detected using the ssi interrupt (ifn = 1) or by interrogating the act status. once started, a 9-bit telegram will always run to completion and will not be prematurely terminated by the sir bit. so, if the sir bit is set to '1' in telegram, the ssi will complete the current transfer and terminate the dialog with an mcl stop condition. figure 62. example of mcl transmit dialog 7654321 76543210a msb lsb tx data 1 tx data 2 msb lsb write stb (tx data 1) sc sd srdy act interrupt (ifn = 0) interrupt (ifn = 1) 0a write stb (tx data 2) sir sdd start stop
64 ATAM894 4679c?4bmcu?03/04 figure 63. example of mcl receive dialog 8-bit pseudo mcl mode in this mode, the ssi exhibits all the typical mcl operational features except for the acknowledge-bit which is never expected or transmitted. mcl bus protocol the mcl protocol constitutes a simple 2-wire bi-directional communication highway via which devices can communicate control and data information. although the mcl proto- col can support multi-master bus configurations, the ssi in mcl mode is intended for use purely as a master controller on a single master bus system. so all reference to multiple bus control and bus contention will be omitted at this point. all data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. normally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. this is then followed by a data telegram, transmitted by the master controller device. this telegram usually contains an 8-bit address code to activate a single slave device connected onto the mcl bus. each slave receives this address and compares it with its own unique address. the addressed slave device, if ready to receive data, will respond by pulling the sd line low during the 9th clock pulse. this represents a so-called mcl acknowledge. the controller detecting this affirmative acknowledge then opens a connection to the required slave. data can then be passed back and forth by the master controller, each 8-bit telegram being acknowledged by the respective recipient. the communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus. 7654321 76543210 a msb lsb tx data 1 rx data 2 msb lsb write stb (tx data 1) sc sd srdy act interrupt (ifn = 0) interrupt (ifn = 1) 0a read srb (rx data 2) sir sdd start stop
65 ATAM894 4679c?4bmcu?03/04 figure 64. mcl bus protocol 1 bus not busy (1) both data and clock lines remain high. start data transfer (2) a high to low transition of the sd line while the clock (sc) is high defines a start condition. stop data transfer (3) a low to high transition of the sd line while the clock (sc) is high defines a stop condition. data valid (4) the state of the data line represents valid data when, after start condition, the data line is stable for the duration of the high period of the clock signal. acknowledge all address and data words are serially transmitted to and from the device in eight-bit words. the receiving device returns a zero on the data line during the ninth clock cycle to acknowledge word receipt. figure 65. mcl bus protocol 2 ssi interrupt the ssi interrupt int3 can be generated either by an ssi buffer register status (i.e., transmit buffer empty or receive buffer full), the end of ssi data telegram or on the fall- ing edge of the sc/sd pins on port 4 (see p4cr). ssi interrupt selection is performed by the interrupt function control bit (ifn). the ssi interrupt is usually used to synchro- nize the software control of the ssi and inform the controller of the present ssi status. the port 4 interrupts can be used together with the ssi or, if the ssi itself is not required, as additional external interrupt sources. in either case this interrupt is capable of waking the controller out of sleep mode. (2) (1) (4) (4) (3) (1) start condition data valid data change data valid stop condition sc sd sc sd start 1n89 1st bit 8th bit ack stop
66 ATAM894 4679c?4bmcu?03/04 to enable and select the ssi relevant interrupts use the ssi interrupt mask (sim) and the interrupt function (ifn) while the port 4 interrupts are enabled by setting appropri- ate control bits in p4cr register. modulation and demodulation if the shift register is used together with timer 2 or timer 3 for modulation or demodula- tion purposes, the 8-bit synchronous mode must be used. in this case, the unused port 4 pins can be used as conventional bi-directional ports. the modulation and demodulation stages, if enabled, operate as soon as the ssi is acti- vated (sir = 0) and cease when deactivated (sir = 1). due to the byte-orientated data control, the ssi (when running normally) generates serial bit streams which are submultiples of 8 bits. an ssi output masking (omsk) func- tion permits, however, the generation of bit streams of any length. the omsk signal is derived indirectly from the 4-bit prescaler of the timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. the number of non-masked data bits is defined by the value pre-pro- grammed in the prescaler compare register. to use output masking, the modulator stop mode bit (msm) must be set to '0' before programming the final data word into the ssi transmit buffer. this in turn, enables shift clocks to the prescaler when this final word is shifted out. on reaching the compare value, the prescaler triggers the omsk signal and all following data bits are blanked. internal 2-wire multi-chip link two additional on-chip pads (mcl_sc and mcl_sd) for the sc and the sd line can be used as chip-to-chip link for multi-chip applications. these pads can be activated by set- ting the mcl bit in the sisc register. they are also used as interface to the internal data eeprom figure 66. multi-chip link figure 67. ssi output masking function scl sda mcl_sc mcl_sd u505m microcontroller v dd bp40/sc bp10 bp43/sd bp13 multi-chip link v ss 8-bit shift register msb lsb shift_cl so control si timer 2 output ssi-control so compare 2/1 4-bit counter 2/1 cl2/1 scl cm1 omsk sc tog2 pout t1out syscl /2
67 ATAM894 4679c?4bmcu?03/04 serial interface registers serial interface control register 1 (sic1) in transmit mode (sdd = 1) shifting starts only if the transmit buffer has been loaded (srdy = 1). setting sir bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). in mcl modes, writing a 0 to sir generates a start condition and writing a 1 generates a stop condition. serial interface control register 2 (sic2) auxiliary register address: '9'hex bit 3bit 2bit 1bit 0 sic1 sir scd scs1 scs0 reset value: 1111b sir s erial i nterface r eset sir = 1, ssi inactive sir = 0, ssi active scd s erial c lock d irection scd = 1, sc line used as output scd = 0, sc line used as input note: this bit has to be set to '1' during the mcl mode and the timer 3 mode 10 or 11 scs1 s erial c lock source s elect bit 1 scs0 s erial c lock source s elect bit 0 note: with scd = '0' the bits scs1 and scs0 are insignificant table 24. serial clock source select bits scs1 scs0 internal clock for ssi 1 1 syscl/2 1 0 t1out/2 01pout/2 0 0 tog2/2 auxiliary register address: 'a'hex bit 3bit 2bit 1bit 0 sic2 msm sm1 sm0 sdd reset value: 1111b msm m odular s top m ode msm = 1, modulator stop mode disabled (output masking off) msm = 0, modulator stop mode enabled (output masking on) ? used in modulation modes for generating bit streams which are not sub multiples of 8 bit. sm1 s erial m ode control bit 1 sm0 s erial m ode control bit 0
68 ATAM894 4679c?4bmcu?03/04 note: sdd controls port directional control and defines the reset function for the srdy-flag serial interface status and control register (sisc) table 25. serial mode control bits mode sm1 sm0 ssi mode 1 1 1 8-bit nrz-data changes with the rising edge of sc 2 1 0 8-bit nrz-data changes with the falling edge of sc 3 0 1 9-bit two-wire mcl mode 4 0 0 8-bit two-wire pseudo mcl mode (no acknowledge) sdd s erial d ata d irection sdd = 1, transmit mode - sd line used as output (transmit data). srdy is set by a transmit buffer write access sdd = 0, receive mode - sd line used as input (receive data). srdy is set by a receive buffer read access primary register address: 'a'hex bit 3bit 2bit 1bit 0 sisc write mcl rack sim ifn reset value: 1111b sisc read - - - tack act srdy reset value: xxxxb mcl m ulti- c hip l ink activation mcl = 1, multi-chip link disabled. this bit has to be set to '0' during transactions to/from the internal eeprom mcl = 0, connects sc and sd, additionally to the internal multi-chip link pads rack r eceive ack nowledge status/control bit for mcl mode rack = 0, transmit acknowledge in next receive telegram rack = 1, transmit no acknowledge in last receive telegram tack t ransmit ack nowledge status/control bit for mcl mode tack = 0, acknowledge received in last transmit telegram tack = 1, no acknowledge received in last transmit telegram sim s erial i nterrupt m ask sim = 1, disable interrupts sim = 0, enable serial interrupt. an interrupt is generated ifn i nterrupt f u n ction ifn = 1, the serial interrupt is generated at the end of telegram ifn = 0, the serial interrupt is generated when the srdy goes low (i.e., buffer becomes empty/full in transmit/receive mode) srdy s erial interface buffer r ea dy status flag srdy = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full srdy = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty act transmission act ive status flag act = 1, transmission is active, i.e., serial data transfer. stop or start conditions are currently in progress. act = 0, transmission is inactive
69 ATAM894 4679c?4bmcu?03/04 serial transmit buffer (stb) ? byte write the stb is the transmit buffer of the ssi. the ssi transfers the transmit buffer into the shift register and starts shifting with the most significant bit. serial receive buffer (srb) ? byte read the srb is the receive buffer of the ssi. the shift register clocks serial data in (most significant bit first) and the loads content into the receive buffer when the complete tele- gram has been received. combination modes the utcm consists of two timers (timer 2 and timer 3) and a serial interface. there is a multitude of modes in which the timers and serial interface can work together. the 8-bit wide serial interface operates as shift register for modulation and demodula- tion. the modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. combination mode timer 2 and ssi figure 68. combination timer 2 and ssi primary register address: '9'hex first write cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb second write cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb primary register address: '9'hex first read cycle bit 7 bit 6 bit 5 bit 4 reset value: xxxxb second read cycle bit 3 bit 2 bit 1 bit 0 reset value: xxxxb 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 pout cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm timer 2 - control tog2 int4 bi-phase manchester modulator output mout t2o timer 2 modulator output-stage t2m2 so control t2c cl2/1 t2i syscl t1out tog3 scl i/o-bus 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o-bus ssi-control tog2 pout t1out syscl mcl_sc mcl_sd transmit buffer receive buffer cm1 i/o-bus pout so scl sc sd dcgo tog2
70 ATAM894 4679c?4bmcu?03/04 combination mode 1: burst modulation ssi mode 1: 8-bit nrz and internal data so output to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler and dcg timer 2 output mode 3: duty cycle burst generator figure 69. carrier frequency burst modulation with the ssi internal data output combination mode 2: bi-phase modulation 1 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler timer 2 output mode 4: the modulator 2 of timer 2 modulates the ssi internal data output to bi-phase code figure 70. bi-phase modulation 1 1 201201201201201201201201201201201201201 dcgo counter 2 tog2 so t2o counter = compare register (= 2) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 tog2 sc so t2o 000 0 00110101 11 1 1 8-bit sr data bit 7 bit 0 data: 00110101
71 ATAM894 4679c?4bmcu?03/04 combination mode 3: manchester modulation 1 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler timer 2 output mode 5: the modulator 2 of timer 2 modulates the ssi internal data output to manchester code figure 71. manchester modulation 1 combination mode 4: manchester modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 5: the modulator 2 of timer 2 modulates the ssi data output to manchester code the 4-bit stage can be used as prescaler for the ssi to generate the stop signal for mod- ulator 2. the ssi has a special mode to supply the prescaler with the shift clock. the control output signal (omsk) of the ssi is used as stop signal for the modulator. this is an example for a 12-bit manchester telegram: figure 72. manchester modulation 2 tog2 sc so t2o 00 0 0011 0101 11 1 1 8-bit sr data bit 7 bit 0 0 bit 7 bit 0 data: 00110101 00000000 123 40 12 0 counter 2/1 = compare register 2/1 (= 4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scli buffer full sir so sc msm timer 2 mode 3 scl counter 2/1 omsk t2o 3
72 ATAM894 4679c?4bmcu?03/04 combination mode 5: bi-phase modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 2 modulator stage timer 2 mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 4: the modulator 2 of timer 2 modulates the ssi data output to bi-phase code the 4-bit stage can be used as prescaler for the ssi to generate the stop signal for mod- ulator 2. the ssi has a special mode to supply the prescaler via the shift clock. the control output signal (omsk) of the ssi is used as a stop signal for the modulator. this is an example for a 13-bit bi-phase telegram. figure 73. bi-phase modulation 00000000 1234 5 0 counter 2/1 = compare register 2/1 (= 5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scli buffer full sir so sc msm timer 2 mode 3 scl counter 2/1 omsk t2o 012
73 ATAM894 4679c?4bmcu?03/04 combination mode timer 3 and ssi figure 74. combination timer 3 and ssi combination mode 6: fsk modulation ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 3 mode 8: fsk modulation with shift register data (so) the two compare registers are used to generate two varied time intervals. the ssi data output selects which compare register is used for the output frequency generation. a '0'-level at the ssi data output enables the compare register 1 and a '1'-level enables the compare register 2. the compare and compare mode registers must be pro- grammed to generate the two frequencies via the output toggle flip-lop. the ssi can be supplied with the toggle signal of timer 2 or any other clock source. the timer 3 counter is driven by an internal or external clock source. 8-bit counter 3 res compare 3/1 t3co1 t3cp t3co2 timer 3 - control t3o cl3 t3i t3ex syscl t1out pout i/o-bus compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu- lator 3 m2 control so tog3 int5 res cm31 t3i t3ex si sc t3m t3cs cp3 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o-bus ssi-control tog2 pout t1out syscl si mcl_sc mcl_sd transmit buffer receive buffer sc sc si
74 ATAM894 4679c?4bmcu?03/04 figure 75. fsk modulation combination mode 7: pulse-width modulation (pwm) ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 3 mode 9: pulse-width modulation with the shift register data (so) the two compare registers are used to generate two varied time intervals. the ssi data output selects which compare register is used for the output pulse generation. in this mode, both compare and compare mode registers must be programmed to generate the two pulse width. it is also useful to enable the single-action mode for extreme duty cycles. timer 2 is used as baud-rate generator and for the triggered restart of timer 3. the ssi must be supplied with the toggle signal of timer 2. the counter is driven by an internal or external clock source. figure 76. pulse-width modulation 01234012340123 counter 3 cm31 cm32 so 401201201201201201201 20123 t3r 40 t3o 1 01 0 000000000 0000 counter 3 cm31 cm32 t3o 00000123456789 101112 13 1415 0 12345 tog2 67 8 1 9 11 12 10 14 13 0 2 3 14 15 0 0 0 1 sir so sco t3r
75 ATAM894 4679c?4bmcu?03/04 combination mode 8: manchester de modulation/pulse-width demodulation ssi mode 1: 8-bit shift register internal data input (si) and the internal shift clock (sci) from the timer 3 timer 3 mode 10: manchester demodulation/pulse-width demodulation with timer 3 for manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. these edges are evaluated by the demodulator stage. the timer stage is used to generate the shift clock for the ssi. a compare register 1 match event defines the correct moment for shifting the state from the input t3i as the decoded bit into the shift register. after that, the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. the compare register 2 can be used to detect a time error and handle it with an interrupt routine. before activating the demodulator mode the timer and the demodulator stage must be synchronized with the bit-stream. the manchester code timing consists of parts with the half bit-length and the complete bit-length. a synchronization routine must start the demodulator after an interval with the complete bit-length. the counter can be driven by any internal clock source. the output t3o can be used by timer 2 in this mode. the manchester decoder can also be used for pulse-width demod- ulation. the input must programmed to detect the positive edge. the demodulator and timer must be synchronized with the leading edge of the pulse. after that a counter match with the compare register 1 shifts the state at the input t3i into the shift register. the next positive edge at the input restarts the timer. figure 77. manchester demodulation 1011100 110 11 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 synchronize manchester demodulation mode timer 3 mode t3ex si sr-data t3i cm31 = sci 100110
76 ATAM894 4679c?4bmcu?03/04 combination mode 9: bi-phase demodulation ssi mode 1: 8-bit shift register internal data input (si) and the internal shift clock (sci) from the timer 3 timer 3 mode 11: bi-phase demodulation with timer 3 in the bi-phase demodulation mode the timer works like in the manchester demodula- tion mode. the difference is that the bits are decoded with the toggle flip-flop. this flip- flop samples the edge in the middle of the bit-frame and the compare register 1 match event shifts the toggle flip-flop output into shift register. before activating the demodula- tion the timer and the demodulation stage must be synchronized with the bit-stream. the bi-phase code timing consists of parts with the half bit-length and the complete bit- length. the synchronization routine must start the demodulator after an interval with the complete bit-length. the counter can be driven by any internal clock source and the output t3o can be used by timer 2 in this mode. figure 78. bi-phase demodulation 011 1 1 01 bit 7bit 6bit 5bit 4bit 3bit 2bit 1 synchronize bi-phase demodulation mode timer 3 mode t3ex q1 = si cm31 = sci sr-data 0000 t3i reset counter 3 101010 bit 0
77 ATAM894 4679c?4bmcu?03/04 combination mode timer 2 and timer 3 figure 79. combination timer 3 and timer 2 combination mode 10: frequency measurement or event counter with time gate timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 compare match toggles (tog2) to the timer 3 timer 3 mode 3: timer/counter; integrated trigger restart and integrated capture (with timer 2 tog2-signal) the counter is driven by an external (t3i) clock source. the output signal (tog2) of timer 2 resets the counter. the counter value before reset is saved in the capture regis- ter. if single-action mode is activated for one or both compare registers, the trigger signal restarts also the single actions. this mode can be used for frequency measure- ments or as event counter with time gate. 8-bit counter 3 res compare 3/1 t3co1 t3cp t3co2 timer 3 - control t3o cl3 t3i t3ex syscl t1out pout i/o-bus compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu- lator 3 control so tog3 int5 res cm31 t3i t3ex tog2 si sci ssi cp3 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout ssi cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm tog2 int4 bi-phase manchester modulator output mout m2 t2o timer 2 modulator 2 output-stage t2m2 control (re, fe, sco, omsk) ssi t2c cl2/1 tog3 syscl t1out scl timer 2 - control m2 t3cs t3m pout dcgo so t2i i/o-bus i/o-bus
78 ATAM894 4679c?4bmcu?03/04 figure 80. frequency measurement figure 81. event counter with time gate combination mode 11: burst modulation 1 timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 compare match toggles the output flip-flop (m2) to the timer 3 timer 3 mode 6: carrier frequency burst modulation controlled by timer 2 output (m2) the timer 3 counter is driven by an internal or external clock source. its compare- and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop. the output toggle flip-flop (m2) of timer 2 is used to enable and disable the timer 3 output. the timer 2 can be driven by the toggle output signal of timer 3 (tog3) or any other clock source. figure 82. burst modulation 1 0012345678 9 10 counter 3 tog2 t3cp- register t3i t3r capture value = 0 capture value = 17 capt. value = 18 11 12131415 16 17 1 2 3 4 5 6 7 8 9 101112 13 14 1516 17 18 0 0 1 23 45 0 01 2 3 4567 8 910 counter 3 tog2 t3cp- register 11 01 2 40 1 t3i 2 3 t3r capture value = 0 capture value = 11 cap. value = 4 0101234501012345010123450101 50101 50101 50101 50101 50101 50101 50101 50101 50101 30 1 2 3 3 0 1 3 2 cl3 counter 3 cm1 cm2 tog3 m3 counter 2/2 tog2 m2 t3o
79 ATAM894 4679c?4bmcu?03/04 combination timer 2, timer 3 and ssi figure 83. combination timer 2, timer 3 and ssi 8-bit counter 3 res compare 3/1 t3co1 t3cp t3co2 timer 3 - control t3o cl3 t3i t3ex syscl t1out pout i/o-bus compare 3/2 t3cm1 t3cm2 t3c t3st modulator 3 demodu- lator 3 control so tog3 int5 res cm31 t3i t3ex tog2 si sci ssi cp3 4-bit counter 2/1 res ovf1 compare 2/1 t2co1 cm1 pout cl2/2 dcg t2m1 p4cr 8-bit counter 2/2 res ovf2 compare 2/2 t2co2 t2cm tog2 int4 bi-phase manchester modulator output mout m2 t2o timer 2 modulator 2 output-stage t2m2 control (re, fe, sco, omsk) t2c cl2/1 tog3 syscl t1out scl timer 2 - control m2 t3cs t3m pout dcgo so t2i i/o-bus i/o-bus 8-bit shift register msb lsb shift_cl so sic1 sic2 sisc scli control stb srb si output int3 i/o-bus ssi-control tog2 pout t1out syscl mcl_sc mcl_sd transmit buffer receive buffer sc si scl
80 ATAM894 4679c?4bmcu?03/04 combination mode 12: burst modulation 2 ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 2 output mode 2: 8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 compare match toggles (tog2) to the ssi timer 3 mode 7: carrier frequency burst modulation controlled by the internal output (so) of ssi the timer 3 counter is driven by an internal or external clock source. its compare- and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop (m3). the internal data output (so) of the ssi is used to enable and disable the timer 3 output. the ssi can be supplied with the toggle signal of timer 2. figure 84. burst modulation 2 combination mode 13: fsk modulation ssi mode 1: 8-bit shift register internal data output (so) to the timer 3 timer 2 output mode 3: 8-bit compare counter and 4-bit prescaler timer 2 output mode 1/6: timer 2 4-bit compare match signal (pout) to the ssi timer 3 mode 8: fsk modulation with shift register data output (so) the two compare registers are used to generate two different time intervals. the ssi data output selects which compare register is used for the output frequency generation. a '0' level at the ssi data output enables the compare register 1 and a '1' level enables the compare register 2. the compare- and compare mode registers must be pro- grammed to generate the two frequencies via the output toggle flip-flop. the ssi can be supplied with the toggle signal of timer 2 or any other clock source. the timer 3 counter is driven by an internal or external clock source. 0101234501012345010123450101 50101 50101 50101 50101 50101 50101 50101 50101 50101 30 1 2 3 3 0 1 3 2 cl3 counter 3 cm31 cm32 tog3 m3 counter 2/2 tog2 so t3o
81 ATAM894 4679c?4bmcu?03/04 figure 85. fsk modulation data eeprom the internal data eeprom offers 2 pages of 512 bits each. both pages are organized as 32 16 bit words. the programming voltage as well as the write cycle timing is gen- erated on chip. if it is necessary to be compatible with the rom parts, only the default page must be used with the flash part. also for compatibility reasons the access to the eeprom is handled via the mcl (serial interface) as in the corresponding rom parts. the page select is performed by either writing ''01h'' (page 1) or ''09h'' (page 0) to the eeprom. figure 86. block diagram eeprom 01234012340123 counter 3 cm31 cm32 so 401201201201201201201 20123 t3r 40 t3o 1 01 0 16-bit read/write buffer address control 8-bit data register eeprom 2 x 32 x 16 hv-generator timing control mode control i/o control scl v dd sda page 1 page 0 --> write "01h" --> write "09h" v ss
82 ATAM894 4679c?4bmcu?03/04 serial interface the eeprom uses an mcl-like two-wire serial interface to the microcontroller for read and write accesses to the data. it is considered to be a slave in all these applications. that means, the controller has to be the master that initiates the data transfer and pro- vides the clock for transmit and receive operations. the serial interface is controlled by the microcontroller which generates the serial clock and controls the access via the scl-line and sda-line. scl is used to clock the data into and out of the device. sda is a bi-directi onal line that is used to transfer data into and out of the device. the following protocol is used for the data transfers. serial protocol data states on the sda-line changing only while scl is low changes on the sda-line while scl is high are interpreted as start or stop condition a start condition is defined as high to low transition on the sda-line while the scl-line is high a stop condition is defined as low to high transition on the sda-line while the scl- line is high each data transfer must be initialized with a start condition and terminated with a stop condition. the start condition wakes the device from standby mode and the stop condition returns the device to standby mode a receiving device generates an acknowledge (a) after the reception of each byte. this requires an additional clock pulse, generated by the master. if the reception was successful the receiving master or slave device pulls down the sda-line during that clock cycle. if an acknowledge is not detected (n) by the interface in transmit mode, it will terminate further data transmissions and go into receive mode. a master device must finish its read operation by a non-acknowledge and then send a stop condition to bring the device into a known state. figure 87. mcl protocol before the start condition and after the stop condition the device is in standby mode and the sda line is switched as input with pull-up resistor. the control byte that follows the start condition determines the following operation. it consists of the 5-bit row address, 2 mode control bits and the read/nwrite bit that is used to control the direction of the following transfer. a '0' defines a write access and a '1' a read access. start condition data valid data change data/ acknowledge valid stop condition scl sda standby standby
83 ATAM894 4679c?4bmcu?03/04 control byte format eeprom the eeprom has a size of 2 512 bits and is organized as 32 x 16-bit matrix each. to read and write data to and from the eeprom the serial interface must be used. the interface supports one and two byte write accesses and one to n-byte read accesses to the eeprom. eeprom - operating modes the operating modes of the eeprom are defined via the control byte. the control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. a '0' defines a write access and a '1' a read access. the five address bits select one of the 32 rows of the eeprom memory to be accessed. for all accesses the complete 16-bit word of the selected row is loaded into a buffer. the buffer must be read or overwritten via the serial interface. the two mode control bits c 1 and c 2 define in which order the accesses to the buffer are performed: high byte ? low byte or low byte ? high byte. the eeprom also supports auto incre- ment and auto decrement read operations. after sending the start address with the corresponding mode, consecutive memory cells can be read row by row without trans- mission of the row addresses. two special control bytes enable the complete initialization of eeprom with '0' or with '1'. write operations the eeprom permits 8-bit and 16-bit write operations. a write access starts with the start condition followed by a write control byte and one or two data bytes from the master. it is completed via the stop condition from the master after the acknowledge cycle. the programming cycle consists of an erase cycle (write ?zeros?) and the write cycle (write ?ones?). both cycles together take about 10 ms. acknowledge polling if the eeprom is busy with an internal write cycle, all inputs are disabled and the eeprom will not acknowledge until the write cycle is finished. this can be used to detect the end of the write cycle. the master must acknowledge polling by sending a start condition followed by the control byte. if the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or per- form further acknowledge polling sequences. if the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. write one data byte write two data bytes write control byte only eeprom address mode control bits read/ nwrite starta4a3a2a1a0 c1 c0 r/nw ackn start control byte ackn data byte ackn data byte ackn stop start control byte a data byte 1 a stop start control byte a data byte 1 a data byte 2 a stop start control byte a stop
84 ATAM894 4679c?4bmcu?03/04 write control bytes a acknowledge; hb: high byte; lb: low byte; r: row address read operations the eeprom allows byte-, word- and current address read operations. the read oper- ations are initiated in the same way as write operations. every read access is initiated by sending the start condition followed by the c ontrol byte which contains the address and the read mode. when the device has received a read command, it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. the master has to acknowledge the received byte if it wants to proceed with the read operation. if two bytes are read out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. the read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. if the memory address limit is reached, the data word address will ?roll over? and the sequential read will continue. the master can terminate the read operation after every byte by not responding with an acknowledge (n) by issuing a stop condition. read one data byte read two data bytes read n data bytes msb lsb write low byte first a4 a3 a2 a1 a0 c1 c0 r/nw row address 0 1 0 byte order lb(r) hb(r) msb lsb write high byte first a4 a3 a2 a1 a0 c1 c0 r/nw row address 1 0 0 byte order hb(r) lb(r) start control byte a data byte 1 n stop start control byte a data byte 1 a data byte 2 n stop start control byte a data byte 1 a data byte 2 a - - - data byte n n stop
85 ATAM894 4679c?4bmcu?03/04 read control bytes a acknowledge, n no acknowledge; hb: high byte; lb: low byte, r: row address initializing the serial interface to the eeprom to prevent unexpected behavior of the eeprom and its interface it is good practice to use an initialization sequence after any reset of the circuit. this is performed by writing: to the serial interface. if the eeprom acknowledges this sequence it is in a defined state. it may be necessary to perform this sequence twice. msb lsb read low byte first, address increment a4 a3 a2 a1 a0 c1 c0 r/nw row address 0 1 1 byte order lb(r) hb(r) lb(r+1) hb(r+1) - - - lb(r+n) hb(r+n) msb lsb read high byte first, address decrement a4 a3 a2 a1 a0 c1 c0 r/nw row address 1 0 1 byte order hb(r) lb(r) hb(r-1) lb(r-1) - - - hb(r-n) lb(r-n) start ?ffh? a n stop
86 ATAM894 4679c?4bmcu?03/04 absolute maximum ratings voltages are given relative to v ss. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . all inputs and outputs are protected against high electrostatic voltages or electric fields. however, precautions to minimize t he build-up of electrostatic charges during handling are recommended. reliability of operation is enhanced if unused inputs are connected to a n appro- priate logic voltage level (e.g., v dd ). parameters symbol value unit supply voltage v dd -0.3 to +6.5 v input voltage (on any pin) v in v ss -0.3 v in v dd +0.3 v output short circuit duration t short indefinite s operating temperature range t amb -40 to +85 c storage temperature range t stg -40 to +130 c soldering temperature (t 10 s) t sld 260 c thermal resistance parameter symbol value unit thermal resistance (sso24) r thja 135 k/w dc operating characteristics v ss = 0 v, t amb = -40c to +85c unless otherwise specified parameters test conditions symbol min. typ. max. unit power supply operating voltage at v dd v dd v por 6.5 v active current cpu active f syscl = 1 mhz v dd = 1.8 v v dd = 3.0 v v dd = 6.5 v i dd 0.2 0.3 0.7 0.4 1.0 ma ma ma power down current (cpu sleep, rc oscillator active, 4-mhz quartz oscillator active) f syscl = 1 mhz v dd = 1.8 v v dd = 3.0 v v dd = 6.5 v i pd 40 70 200 150 a a a sleep current (cpu sleep, 32-khz quartz oscillator active 4-mhz quartz oscillator inactive) v dd = 1.8 v v dd = 3.0 v v dd = 6.5 v i sleep 0.4 0.6 0.8 1.5 2.0 a a a sleep current (cpu sleep, 32-khz quartz oscillator inactive 4-mhz quartz oscillator inactive) v dd = 3.0 v v dd = 6.5 v i sleep 0.3 0.6 1.0 1.8 a a pin capacitance any pin to v ss c l 710pf
87 ATAM894 4679c?4bmcu?03/04 note: the pin bp20/nte has a static pull-up resistor during the reset-phase of the microcontroller power-on reset threshold voltage por threshold voltage bot = 1 v por 1.54 1.7 1.88 v por threshold voltage bot = 0 v por 1.83 2.0 2.20 v por hysteresis v por 50 mv voltage monitor threshold voltage vm high threshold voltage v dd > vm, vms = 1 v mthh 3.0 3.35 v vm high threshold voltage v dd < vm, vms = 0 v mthh 2.77 3.0 v vm middle threshold voltage v dd > vm, vms = 1 v mthm 2.6 2.9 v vm middle threshold voltage v dd < vm, vms = 0 v mthm 2.4 2.6 v vm low threshold voltage v dd > vm, vms = 1 v mthl 2.2 2.44 v vm low threshold voltage v dd < vm, vms = 0 v mthl 2.0 2.2 v external input voltage vmi v dd = 3 v, vms = 1 v vmi 1.3 1.4 v vmi v dd = 3 v, vms = 0 v vmi 1.18 1.3 v all bi-directional ports input voltage low v dd = 1.8 to 6.5 v v il v ss 0.2 v dd v input voltage high v dd = 1.8 to 6.5 v v ih 0.8 v dd v dd v input low current (switched pull-up) v dd = 2.0 v, v dd = 3.0 v, v il = v ss v dd = 6.5 v i il -3 -10 -80 -8 -20 -150 -14 -40 -240 a a a input high current (switched pull-down) v dd = 2.0 v, v dd = 3.0 v, v ih = v dd v dd = 6.5 v i ih 3 10 60 6 20 100 14 40 160 a a a input low current (static pull-up) v dd = 2.0 v v dd = 3.0 v, v il = v ss v dd = 6.5 v i il -30 -80 -300 -50 -160 -700 -98 -320 -1200 a a a input low current (static pull-down) v dd = 2.0 v v dd = 3.0 v, v ih = v dd v dd = 6.5 v i ih 20 80 300 50 160 600 100 320 1000 a a a input leakage current v il = v ss i il 100 na input leakage current v ih = v dd i ih 100 na output low current v ol = 0.2 v dd v dd = 2.0 v v dd = 3.0 v, v dd = 6.5 v i ol 0.9 3 8 1.8 5 15 3.6 8 22 ma ma ma output high current v oh = 0.8 v dd v dd = 2.0 v v dd = 3.0 v, v dd = 6.5 v i oh -0.8 -3 -8 -1.7 -5 -15 -3.4 -8 -24 ma ma ma dc operating characteristics (continued) v ss = 0 v, t amb = -40c to +85c unless otherwise specified parameters test conditions symbol min. typ. max. unit
88 ATAM894 4679c?4bmcu?03/04 ac characteristics supply voltage v dd = 1.8 to 6.5 v, v ss = 0 v, t amb = 25c unless otherwise specified. parameters test conditions symbol min. typ. max. unit operation cycle time system clock cycle v dd = 1.8 to 6.5 v t amb = -40 to 85 c t syscl 500 2000 ns v dd = 2.4 to 6.5 v t amb = -40 to 85 c t syscl 250 2000 ns timer 2 input timing pin t2i timer 2 input clock f t2i 5mhz timer 2 input low time rise/fall time < 10 ns t t2il 100 ns timer 2 input high time rise/fall time < 10 ns t t2ih 100 ns timer 3 input timing pin t3i timer 3 input clock f t3i syscl/2 mhz timer 3 input low time rise/fall time < 10 ns t t3il 2t syscl ns timer 3 input high time rise/fall time < 10 ns t t3ih 2t syscl ns interrupt request input timing interrupt request low time rise/fall time < 10 ns t irl 100 ns interrupt request high time rise/fall time < 10 ns t irh 100 ns external system clock exscl at osc1, ecm = en rise/fall time < 10 ns f exscl 0.5 4 mhz exscl at osc1, ecm = di rise/fall time < 10 ns f exscl 0.02 4 mhz input high time rise/fall time < 10 ns t ih 0.1 s reset timing power-on reset time v dd > v por t por 1.5 5 ms rc-oscillator 1 frequency f rcout1 3.8 mhz stability v dd = 2.0 to 6.5 v t amb = -40 to 85 c ? f/f 50 % rc-oscillator 2 - external resistor frequency r ext = 180 k ? f rcout2 4mhz stability v dd = 2.0 to 6.5 v t amb = -40 to 85 c ? f/f 15 % stabilization time t s 10 s 4-mhz crystal oscillator (operating range v dd = 2.2 v to 6.5 v) frequency f x 4mhz start-up time t sq 5ms stability ? f/f -10 10 ppm integrated input/output capacitances (configurable) c in /c out programmable c in c out 0, 2, 5, 7, 10 or 12 0, 2, 5, 7, 10 or 12 pf pf
89 ATAM894 4679c?4bmcu?03/04 crystal characteristics figure 88. crystal equivalent circuit 32-khz crystal oscillator (operating range v dd = 2.0 v to 6.5 v) frequency f x 32.768 khz start-up time t sq 0.5 s stability ? f/f -10 10 ppm integrated input/output capacitances (configurable) c in /c out programmable c in c out 0, 2, 5, 7, 10 or 12 0, 2, 5, 7, 10 or 12 pf pf external 32-khz crystal parameters crystal frequency f x 32.768 khz serial resistance rs 30 50 k ? static capacitance c 0 1.5 pf dynamic capacitance c1 3 ff external 4-mhz crystal parameters crystal frequency f x 4.0 mhz serial resistance rs 40 150 ? static capacitance c 0 1.4 3 pf dynamic capacitance c1 3 ff data eeprom operating current during erase/write cycle i wr 600 1300 a endurance erase-/write cycles t amb = 85c e d e d 200000 20000 500000 cycles cycles data erase/write cycle time for 16-bit access t dew 913ms data retention time t amb = 85c t dr t dr 100 10 years years power-up to read operation t pur 0.2 ms power-up to write operation t puw 0.2 ms program eeprom erase-/write cycles, t amb = 0 to 40c n ew 100 1,000 cycles serial interface scl clock frequency f sc_mcl 100 500 khz ac characteristics (continued) supply voltage v dd = 1.8 to 6.5 v, v ss = 0 v, t amb = 25c unless otherwise specified. parameters test conditions symbol min. typ. max. unit l c 1 r s c 0 oscin oscout equivalent circuit sclin sclout
90 ATAM894 4679c?4bmcu?03/04 emulation the basic function of emulation is to test and evaluate the customer's program and hardware in real time. this therefore enables the analysis of any timing, hardware or software problem. for emulation purposes, all marc4 controllers include a special emulation mode. in this mode, the internal cpu core is inactive and the i/o buses are available via port 0 and port 1 to allow an external access to the on-chip peripherals. the marc4 emulator uses this mode to control the peripherals of any marc4 control- ler (target chip) and emulates the lost ports for the application. the marc4 emulator can stop and restart a program at specified points during execu- tion, making it possible for the applications engineer to view the memory contents and those of various registers during program execution. the designer also gains the ability to analyze the executed instruction sequences and all the i/o activities. figure 89. marc4 emulation marc4 target chip core (inactive) p o r t 1 p o r t 0 application-specific hardware peripherals marc4 emulator program memory trace memory control logic personal computer core marc4 emulation-cpu i/o control i/o bus port 0 port 1 syscl/ tcl, te, nrst emulation control emulator target board
91 ATAM894 4679c?4bmcu?03/04 package information ordering information extended type number (1) program memory data-eeprom package delivery ATAM894x-tnq 8 kb flash 2 512 bit sso24 taped and reeled ATAM894x-tns 8 kb flash 2 512 bit sso24 tubes note: 1. x = hardware revision technical drawings according to din specifications package sso24 dimensions in mm 8.05 7.80 0.15 0.05 0.25 0.65 7.15 1.30 5.7 5.3 4.5 4.3 6.6 6.3 0.15 24 13 112
92 ATAM894 4679c?4bmcu?03/04 revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. changes from rev. 4679b - 07/03 to rev. 4679c - 03/04 1. put datasheet in a new template. 2. figure 1 ?block diagram? on page 1 changed. 3. table 9 ?pheripheral addresses? on page 23 changed. 4. section ?features? on page 35 changed. 5. table 19 ?timer 2 output select bits? on page 44 changed. 6. new heading rows at table ?absolute maximum ratings? on page 86 added. 7. table ?thermal resistance? on page 86 changed 8. section ?emulation? on page 90 added. 9. table ?ordering information? on page 91 deleted. 10. table ?ordering information? on page 92 changed.
93 ATAM894 4679c?4bmcu?03/04 table of contents features................................................................................................. 1 description ............................................................................................ 1 pin configuration.................................................................................. 2 pin description ..................................................................................... 2 introduction........................................................................................... 3 differences between ATAM894 and atarx90/x92............................ 3 program memory .................................................................................................. 3 configuration memory .......................................................................................... 3 data memory ........................................................................................................ 3 reset function...................................................................................................... 3 marc4 architecture............................................................................. 4 general description .............................................................................................. 4 components of marc4 core ............................................................................... 4 program memory ............................................................................................5 ram ................................................................................................................5 registers .........................................................................................................6 alu .................................................................................................................8 i/o bus ............................................................................................................8 instruction set .................................................................................................9 interrupt structure ...........................................................................................9 interrupt processing ........................................................................................9 interrupt latency .............................................................................................9 master reset ...................................................................................................... 11 power-on reset and brown-out detection ....................................................12 watchdog reset ...........................................................................................13 external clock supervisor .............................................................................13 voltage monitor................................................................................................... 13 voltage monitor control/ status register ......................................................14 clock generation ................................................................................................ 15 clock module ................................................................................................15 oscillator circuits and external clock input stage .......................................17 clock management .......................................................................................19 power-down modes ............................................................................................ 21 peripheral modules............................................................................. 22 addressing peripherals....................................................................................... 22 bi-directional ports.............................................................................................. 24 bi-directional port 1 .......................................................................................24 bi-directional port 2 .......................................................................................25 bi-directional port 5 .......................................................................................26
94 ATAM894 4679c?4bmcu?03/04 bi-directional port 4 .......................................................................................28 bi-directional port 6 .......................................................................................30 universal timer/counter/ communication module (utcm) ............................... 31 timer 1 ..........................................................................................................32 timer 2 ..........................................................................................................35 timer 3 ..........................................................................................................46 synchronous serial interface (ssi) ...............................................................58 combination modes ......................................................................................69 data eeprom ..................................................................................... 81 serial interface.................................................................................................... 82 serial protocol ...............................................................................................82 eeprom ......................................................................................................83 absolute maximum ratings............................................................... 86 thermal resistance............................................................................ 86 dc operating characteristics............................................................ 86 ac characteristics.............................................................................. 88 ordering information.......................................................................... 91 package information .......................................................................... 91 revision history ................................................................................. 92
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